How much tolerance has Rigol in component value selection to get the PLL sorted?
Is the range of values within the normal +-% tolerance of components around the PLL or have they just got the basic values wrong?
Sure we would normally use NPO here, maybe they didn't?
No it is not component values tolerance issue, as you said they got the basic values wrong.
The worst problem that I see is they did not follow the manufacturer's recommendations, they even did not stick to the datasheet, why is I have no idea. Imagine yourself designing something, you select a part and the part manufacturer says - we make it easier for you, we have done extensive testing in the Lab an we have a reference design you can use. We have a set of recommended settings and that will guarantee the part will perform to specification. Noone knows our part better than us, the manufacturer. We have a simulator that you can use, here it is, take it, just run it and you will have your design in less than 10 minutes and it will guarantee to work. And you say like "Meh, I'll do it my way, have no idea how yet but will try random values until I get bored and then the heck with it as long as the device appear to be working".
Show a screenshot of their ADC clock (page 19 of this thread) to any engineer familiar with ADC applications and watch his reaction: