Rigol has created updated firmware for the MSO1000Z and DS1000Z series of scopes in immediate response to the issues found by Dave and the EEVBlog community.
Firmware has passed the engineering and applications tests and is proceeding to the full suite of testing to go into production. We expect the final firmware for the MSO1000Z and DS1000Z series to be released by December 19th with the MSO2000A, DS2000A, and DS2000 firmware to follow and to be available by toward the end of December.
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So Chris, is Rigol still going to release the final firmware for the DS1000Z series today (19 December)?
If not, when do you think there will be a solution available for those of us who are experiencing 70ns or more jitter?
Maybe a chance to at least reload the previous firmware which was not so bad?
I hope to hear back from you on this soon and with some good news.
so far I have heard this..
<crickets>
In the meantime I contacted the EU representative for Rigol, asking for the latest firmware.
I saw here in this thread that some people have got scopes with later f/w than the beta.
My reply from the EU rep:
"Dear poida_pie
Normally Update requests from Australia are handled directly from China,
But you already have the latest available firmware installed.
so I took over to tell you that.
Best regards
Thomas Rottach
Application Engineer
Rigol Technologies EU GmbH
"
So, the latest f/w exists
https://www.eevblog.com/forum/testgear/new-rigol-ds1054z-oscilloscope/msg571343/#msg571343but evidently it's not available for distributors to offer to existing customers.
But not to worry, it's a cultural thing, according to Marmad
https://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg571463/#msg571463so sit back, relax and shut the fuck up Mr Poida_pie.
By the way, would anyone here consider buying my DS1054Z, and if so, at what discount from new price.
I am wondering just how little it is worth, with it's 70ns jitter at about 35us horizontal delay.
Or time to go animal with it (RoTTe will agree)
Time to read up on the ADF4360-7 and it's loop filter. It's not as if Rigol design guys felt the need to.
First and likely most ignorant guess would be to re-implement the filter with a trim cap set to the existing value of C2. Fiddle with that
while watching the pll lock output on pin 20 (or whatever it was, this is from memory).