Yes there is a common issue with DS 2000 . The AC coupling trigger jitter.
Only yours and mine are worse after beta?
MarkL, i'll check tomorrow if i can get second scope here. If not i'll try to probe itself without blowing it up
As for instability in the clock, my first thought after watching the video was whether using external low-drifting clock (like rubidium standard) would do any difference to the jitter issue on ds1000z series.
Yes there is a common issue with DS 2000 . The AC coupling trigger jitter.Where are talking about the PLL jitter issue in this topic. The AC coupling jitter issue has nothing to do with PLL instability in the DS1000z. I'm not sure why you bring this up. Are you simply trolling now ?
Totally agree. In my case, Chris and team "upgraded" the firmware on my scope while they had it at their facility to use in investigating a network bug. So I had no choice in the matter. My only plan for this scope is to sell it. First that was delayed waiting for Chris and Steve to return it. Now that is delayed waiting for a firmware that doesn't randomly lock up the scope (WORSE than the situation before I sent it in for "repair").Are you saying you can't simply downgrade the firmware via the bootloader method on the DS2000? Afaik, this would be a first for the DS2000 series.
I don't really know about the bootloader history/availability on the DS1000Z series (there is no reference to it that I can find), but if what you're saying is true, it negates the Rigol published and long-circulated document, "DS2000 DS4000 DS6000 Firmware Upgrade Procedure".
Well the PLL in a DS2000 runs at 2GHz, the one in the DS1000z on 1 GHz, also we don't know the loop filter component values of the DS2000 and we don't know how the chip is programmed.
But I really doubt there is a similar problem that needs fixing on the DS2000 since is no jitter on these beauties.
Only yours and mine are worse after beta?
That is sufficient to say the beta did not correct the issue.
Please offer a reasonable explanation why AC coupled trigger issue had not been addressed for two years and all of a sudden a fix was announced in beta when we pointed out to the problem with the PLL.
And please offer a reasonable explanation why Rigol was quick to announce DS2000 will be also updated for AC coupled trigger issue.
Although not as definitive, you might also be able to examine a long-point FFT taken with the scope of a known stable source (like a crystal oscillator). If the sample clock is unstable you should see modulation in the FFT. I'm not familiar with how many points the various Rigol models use for it's internal FFT calculations, so I would download the long raw waveform capture and process it externally. Obviously this doesn't involve taking the scope apart, and it might be a good starting point that would show if there's any egregious problem. However, it's still not proof the PLL is locked.
Please offer a reasonable explanation why AC coupled trigger issue had not been addressedWell, I don't know if the problems are related, but the answer to these questions is blatantly obvious. Dave made a video decrying the bug(s) which has garnered a bunch of attention - period.
Is it a case of 'The squeaky wheel gets the Oil' ?
MarkL, i'll check tomorrow if i can get second scope here. If not i'll try to probe itself without blowing it up
As for instability in the clock, my first thought after watching the video was whether using external low-drifting clock (like rubidium standard) would do any difference to the jitter issue on ds1000z series.
Thank you Sergey, will wait for your test results.
As to external clock, rubidium standards put out 10-15MHz , so you cannot just use one for the scope, you may still need to use a PLL and reference it from that low frequency standard. For the 1Ghz clock i just built i used a low jitter integrated TCXO. Sufficient for the purpose.
MarkL, what did you use to download large waveform samples? I tried a software praised in another thread but i only get 1k samples or something, though i set a large memory buffer on the scope. Is a SCPI command for it?
Thanks Sergey. Even with the 20MHz bandwidth limit it is still 12dB or more worse noise than my homebrewed PLL. Would be interesting to look at the spectral chart.
You might have better luck saving the waveform to the USB drive, but I didn't try it. If this still doesn't do it for you, I can try and clean up the octave code a little.