MarkL - thanks a bunch for the work you have done, we are fortunate to have you here with all your nice test equipment, except the Rigol scope which is itself being under test.
So we can now say the RCC (Rigol Chaos Clock) is not limited to just channel input signal sampling and is propagated to the downstream bus, causing whatever damage. By other words, until Rigol delivers the proper fix,
YOU GUYS CANNOT TRUST YOUR RIGOL SCOPE
Such a fix would be a change that will get the ADF4360-7 PLL (ADC clock source) to generate the proper 1GHz signal. I have attached a side by side screenshots again what it is now and what it has to be. Can this be done without a hardware change - I personally doubt but that is IMHO.
Here is what the ADC datasheet says in regards to clock:
...The quality of the input clock is extremely important for high-speed, high-resolution ADCs
...If the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the ADC clock input.