Precision matched transistors on a monolithic process use an interleaved layout to cancel out the effects of process variation. For duals and quads which are advertised to have matched parameters, I think this means that a symmetrical and mirrored layout is used with all of the matched transistors interleaved with each other.
Matched transistors which use interleaving are not suitable for high frequency applications because of capacitive coupling between the transistors, and I suspect this affects short term settling time as well although long term setting time will be improved by better thermal balancing.