EEVblog #496 - What Is An FPGA?

[WarSim]

Just get the de0 nano.

Great I will look that one up. 

[WarSim]

Here is my CycloneIII prototype board that I made year and a half ago. I remember I cut my finger badly while trying to drill a hole in SMT adapter to connect bottom pad of the QFP to the ground. Whole bunch of decoupling caps soldered on other side (not shown). Chip in the corner is CPLD, MAX from Altera - I killed it by reprogramming too many times. Rainbow ribbon cable toing to ADC extension board that only works at 10-15MHz due to lack of bus transeivers and poor signal integrity.
Still I had much more fun with this design than with complete dev board - I can solder and un-solder things at will.

The dev board is to test the software setup.  Once I can confirm the OS quirks are not going to get in the way.  I will make an experiment board with the smallest FPGA it can support. 
Just because putting a project in a huge chip isn't a big enough challenge for me.  The most fun I have had with PICs was figuring out how to make a 6 pin PIC10 do more with so few pins and low power.  And lately put a display driver in a PIC24, when everyone I have run into says it has to be done in an FPGA or dedicated display driver IC. 

[Rubi]

Awesome introduction.
Please bring more of this stuff.

http://rubines.blogspot.co.at/

[AndyC_772]

Found a prices for the USB blaster was a bit dear, but found a MAX II CPLD dev kit for half the price that includes a USB blaster. 

The genuine Altera USB Blaster cable is stupidly expensive, but I've had no problems at all with a couple of 3rd party copies from China that cost next to nothing. Some of them also come with a handy little Cyclone II dev board that has a voltage regulator, configuration device and crystal on it, and all the FPGA pins broken out to 0.1" headers.

For example:
http://www.ebay.co.uk/itm/Altera-CycloneII-EP2C5T144-FPGA-Board-USB-Blaster-JTAG-/121104246158?pt=UK_Computing_Other_Computing_Networking&hash=item1c3260258e

[Chet T16]

My $50 saleae logic analyser clone can be configured as a USB blaster

[jahonen]

With all of that said, I'm a hardware guy and love FPGAs...  Keep the videos coming!

I'm a software guy and I love FPGAs too In VHDL you can even use variables, procedures, functions and loops. But you have to keep in mind that it needs A LOT of logic units, because a loop is kind of unrolled and synthesized in parallel, same for procedures and functions. You have to sequence it with state machines from time to time, when it gets to big or when the timing requirements are not met anymore because of too long logic chains. Hardware guys don't like my VHDL code

I am a hardware/VHDL/Altera guy and I absolutely do not like the style VHDL is usually (at least what I have seen too many times in my work, so excuse my mini-rant) written.

Why everybody seems to insist on writing "clk'event and clk='1'" instead of more clear function "rising_edge(clk)"? Another thing is that most (V)HDL designers seem to be fans of cryptic magic numbers expressed in most inconvenient base and use them everywhere in the code which makes it unnecessarily difficult/impossible to maintain and reuse. For example, try to change clock frequency of a design which has clock cycle counts embedded that way in the code to produce a certain timing in seconds. Another thing is that use of variables (depending on the context, variables can be a "wire" or a "reg" in verilog terms) as "local signals" in processes seem to be non-existing, which would make it easy to duplicate/reuse the process without inventing new signal names or doing other refactoring and cluttering the design.

Most of the time the functions, procedures, records etc in VHDL do not actually make any more complex logic result, but they make the code much more readable and reusable if used properly.

Oh, and one simple pitfall of the FPGA design is that any external asynchronous signal, i.e. a signal which has no guaranteed timing referenced to a clock which FPGA logic is internally using, must be synchronized (using a chain of DFF's) separately to the internal clock. Failing to do that can cause much head-scratching (been there, done that!), as the system might react in completely unexpected way to that. If one looks at IO structures of a MCU, there usually is this kind of structure, so with MCUs one can live happily without ever stomping on this issue.

Regarding the timing stuff, TimeQuest timing analyzer is extremely useful part of Altera Quartus and is worth of getting familiar with (but you can definitely do "led-blinkers" without ever caring about it!). One should at least tell the clock frequency to it which the chip operates, so it can give a pretty good judgement if the design works or not. It can automatically derive PLL output clocks from PLL input clocks with "derive_pll_clocks" magic word in the .sdc file.

And finally, the SignalTap is extremely useful and versatile, I have even used a simple FPGA board and SignalTap as an substitute for a real logic analyzer, worked just fine

Regards,
Janne

[Unixon]

No doubt, FPGAs are awesome, but one thought always comes up as this is being discussed.
A hobbyist to hobbyist question: What would YOU do with an FPGA ?
Something that is not there yet or even unseen and unheard of ...

[kbecker]

For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.
There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.

In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.
Check it out at http://pshdl.org or the new and much more advanced editor at http://beta.pshdl.org
There is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!

If you have any questions about it feel free to contact me.

[ChrisW]

No doubt, FPGAs are awesome, but one thought always comes up as this is being discussed.
A hobbyist to hobbyist question: What would YOU do with an FPGA ?
Something that is not there yet or even unseen and unheard of ...

Hardware hacking.

Developing custom drivers for things like RGB LEDS. I really want to develop my own screen capable of video playback, something which cant be done with an arduino or other bog standard MCU, they simply are not fast enough.

The list goes on.

But first, gotta learn to walk before I can run.

-Chris

[WarSim]

My $50 saleae logic analyser clone can be configured as a USB blaster

I have one of those but I bought mine when they cost $99.00

[MasterOfNone]

For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.
There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.

In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.
Check it out at http://pshdl.org or the new and much more advanced editor at http://beta.pshdl.org
There is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!

If you have any questions about it feel free to contact me.

I had a look at your website and I remembered doing CPLD designs using ‘Abel’ and having to handwrite state machines to do the main sequential processing.
One of the problems with ‘Abel’ was that engineers really needed to know about Digital Design if they wanted to use it for things more complex than the typical Address decoding etc. One of the problems would be knowing about things like Metastability, especially if your design has multiple clocks.  Looking at PSHDL (only briefly) is was wondering if it hasn’t reintroduced some of the issues which no longer seem to be a problem with current two main HDL’s.

[AndyC_772]

Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.

I've lost count of the number of times I've written code like:

Code: [Select]

IF clk'event AND clk = '1' THEN
    interesting_signal_meta <= interesting_signal;
    IF interesting_signal_meta = '0' THEN
        do one thing...;
    ELSE
        do some other thing...;
    END IF;
END IF;


[John Coloccia]

Just an FYI, clk'event and rising_edge are not equivalent.  rising_edge specifically looks for a transition 0 (and other things) to 1, whereas old style just checked that clk was 1.  While new designs should probably use rising_edge, if you went back and changed all of your old designs you might well run into different behavior, especially in your simulations.

[FrankBuss]

Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.

I've lost count of the number of times I've written code like:

Code: [Select]

IF clk'event AND clk = '1' THEN
    interesting_signal_meta <= interesting_signal;
    IF interesting_signal_meta = '0' THEN
        do one thing...;
    ELSE
        do some other thing...;
    END IF;
END IF;


Right, this helps for metastability. But the main problem with asynchronous external signals are setup/hold time violations. For example "interesting_signal" has value 1 and some logic driven by it uses this right after the rising clock edge, but other logic uses it half a clock cycle later and then it might be 0, which leads to interesting problems. Using an input latch as you did, helps for this too.

[jahonen]

Metastability: a pain in the backside if you don't really know what it is and how to work around it, but really not that big a deal once you understand the circumstances under which it can bite.

I've lost count of the number of times I've written code like:

Code: [Select]

IF clk'event AND clk = '1' THEN
    interesting_signal_meta <= interesting_signal;
    IF interesting_signal_meta = '0' THEN
        do one thing...;
    ELSE
        do some other thing...;
    END IF;
END IF;


Yes, that is a way around it. But standard practice (as mentioned in Howard Johnson's HSDD book) would need something like 2-3 DFF's cascade to get low enough probability for metastable event. But of course that depends on how often the input signal toggles. So in practice I have made a component which I instantiate whenever I need such a thing, and can be easily configured for different chain lengths. That contains all necessary precautions, like adding synthesis attributes for identifying such a synchronizer.

Code: [Select]

signal sreg : std_logic_vector(SYNC_STAGES-1 downto 0);
attribute altera_attribute of sreg : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED";

Of course Quartus is pretty good at figuring that synchronizer anyway, but it doesn't hurt to tell that explicitly to prevent it from touching it.

Regards,
Janne

[AndyC_772]

That's the point I was trying to make... nothing in the FPGA uses interesting_signal directly apart from the input to the latch. Everything else uses interesting_signal_meta, which (we presume!) has settled to a definite 1 or 0 by the time of the clock pulse immediately after the one on which it latches interesting_signal.

In some cases - perhaps if the clock speed is high, or the FPGA is particularly susceptible to this effect - it can be a good idea to cascade two or more latches. I know Altera give the option of 1, 2 or more synchronisation stages on their dual-port SRAMs for this reason, though I've never personally needed more than one stage.

[MasterOfNone]

That's the point I was trying to make... nothing in the FPGA uses interesting_signal directly apart from the input to the latch. Everything else uses interesting_signal_meta, which (we presume!) has settled to a definite 1 or 0 by the time of the clock pulse immediately after the one on which it latches interesting_signal.

In some cases - perhaps if the clock speed is high, or the FPGA is particularly susceptible to this effect - it can be a good idea to cascade two or more latches. I know Altera give the option of 1, 2 or more synchronisation stages on their dual-port SRAMs for this reason, though I've never personally needed more than one stage.

I believe that if wrote something similar in PSHDL then the assignment and check condition would always be done in parallel. I think you’ll need to write you own state machines for sequential operations, and if you have multiple state machines on different clocks then things could get interesting. But I didn’t spend that much time looking at PSHDL and it probably has some elegant solutions for these types of problems.

[PuterGeek]

...Throw that at the little PIC or AVR and this is what will happen :
it will jump out of its socket , scamper to the far corner of your circuit board , roll over on it's back , curl up it's tiny little legs and simply die...

ROF, LMAO! 

[PuterGeek]

...You should see his photography setupthis is the machine doing it :
http://www.flickr.com/photos/fotoopa_hs/sets/72157627714453063/
driven by a single cyclone FPGA.

Impressive equipment and photos as well as a perfect example! 

[jridley]

coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953

[vk6hdx]

Great video Dave, thanks! 

[jahonen]

Just an FYI, clk'event and rising_edge are not equivalent.  rising_edge specifically looks for a transition 0 (and other things) to 1, whereas old style just checked that clk was 1.  While new designs should probably use rising_edge, if you went back and changed all of your old designs you might well run into different behavior, especially in your simulations.

While it is true that they are not exactly equivalent, but I think that for most purposes, both work just fine. But let's actually take a look what rising/falling_edge() functions contain, as the source is available from IEEE (http://standards.ieee.org/downloads/1076/1076-2008/):

Code: [Select]

  -------------------------------------------------------------------   
  -- edge detection
  -------------------------------------------------------------------   
  function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
  begin
    return (s'event and (To_X01(s) = '1') and
            (To_X01(s'last_value) = '0'));
  end function rising_edge;

  function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
  begin
    return (s'event and (To_X01(s) = '0') and
            (To_X01(s'last_value) = '1'));
  end function falling_edge;

and to_x01() & cvt_to_x01():

Code: [Select]

 
  --------------------------------------------------------------------
  function To_X01 (s : STD_ULOGIC) return X01 is
  begin
    return (cvt_to_x01(s));
  end function To_X01;

  constant cvt_to_x01 : logic_x01_table := (
    'X',                                -- 'U'
    'X',                                -- 'X'
    '0',                                -- '0'
    '1',                                -- '1'
    'X',                                -- 'Z'
    'X',                                -- 'W'
    '0',                                -- 'L'
    '1',                                -- 'H'
    'X'                                 -- '-'
    );

So in essence, they convert the 9-valued logic state to simpler X01-form and then do principally the same thing. So unless one uses L or H signal levels in the clock signal, both should work just fine. For example, rising_edge(clk)-function detects a transition from L to H state as a rising edge, while clk'event and clk='1' does not.

Regards,
Janne

[MacAttak]

coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953

It's a decent starter board. I have one. Slightly less capable than the DE0-Nano, but also slightly less expensive.

[Alexei.Polkhanov]

coincidentally, SparkFun just released an FPGA dev board for $75 US:
https://www.sparkfun.com/products/11953

These are not "development boards", these are just breakout boards for Spartan or Cyclone, they may have clock source, JTAG connector, perhaps something else, but calling that a complete dev board will be little bit of stretch IMHO.
Plenty other breakout boards available on Ebay. This one I think has few bypass caps missing but it is definitely saves you trouble of soldering BGA http://www.ebay.com/itm/EP4CE10F17C8N-EP4CE10-FPGA-ALTERA-Cyclone-IV-Evaluation-Development-Core-Board-/251247908829?pt=LH_DefaultDomain_0&hash=item3a7f8ad7dd

Breakout board is one that has minimum components, power supply, clock, bypass caps but it is intended to be soldered or plugged into socket on another bigger board designed for specific application. Voltage controlled oscillator, or GSM module are other examples of breakout boards.

Dev board is opposite - it meant to be used separately and extensions are added to dev board itself.

Speaking of FPGA breakout boards I wish there were more of these available for prototyping especially with latest FPGAs.

[gregariz]

For those of you that don't like to learn VHDL or Verilog, I developed a new language that focuses on being more C-like and easier to learn. It is called PSHDL.
There is also a Web UI where you can code online and get the generated code. In the near future you will also be able to simulate your code in your browser, but that currently only works in Dartium. But you can also generate C and Java Code out of it for simulation purposes.

In PSHDL you still have to learn how to "program" hardware, but at least a few common mistakes that are easy to make with VHDL or Verilog are avoided.
Check it out at http://pshdl.org or the new and much more advanced editor at http://beta.pshdl.org
There is also a blog and twitter to follow the development of it. The ultimate aim is to generate the Arduino for FPGAs!

If you have any questions about it feel free to contact me.

I had a look at your website and I remembered doing CPLD designs using ‘Abel’ and having to handwrite state machines to do the main sequential processing.
One of the problems with ‘Abel’ was that engineers really needed to know about Digital Design if they wanted to use it for things more complex than the typical Address decoding etc. One of the problems would be knowing about things like Metastability, especially if your design has multiple clocks.  Looking at PSHDL (only briefly) is was wondering if it hasn’t reintroduced some of the issues which no longer seem to be a problem with current two main HDL’s.

Last time I looked Xilinx's ISE integrated ABEL into its design flow, although they no longer actively promote it, its still perfectly usable - particularly for Hardware designers who I suspect are still the main users. Metastability is still an issue out there today with VHDL. IMO ABEL's main problem was that VHDL came along as a standardized open language while most of the HDL's back in the 80's and 90's were somewhat proprietary. By version 5 Abel was doing some pretty good stuff. Today we really only have Xilinx, Lattice and Altera who swallowed most of the smaller players long ago including DataIO. The ones they didnt swallow died.. along with their languages.