- same FPGA
That one's a bit of a stretch, the only thing you can get on that is theoretical maximum gate speed, but they have to be programmed.
it didn't matter what "program" inside the FPGA, the i/o jitter on non-dedicated "clock out" pins will be always the same. Sure, i/o standard could have influence as well, but both DSO are using the same ADC / parallel clock termination so we can ignore it. It depends as well on input clock jitter, and for sure was Rigol smart and used dedicated quarz+inverter combination to archieve low jitter, but then they ruined by using another one inverter gate to drive the FPGA. Tekway is using directly crap quarz oscillator.
Whatever both used, it is not good enought^^. No matter what design inside FPGA, the output clock for ADCs will have max 650ps period jitter. So even when we ignore the i/o skew on FPGA, we will have up to 1.3ns period jitter worst case between 2 output clocks. Rigol is using 10ADCs, so 5 clocks (+5 inverted). Tekway is using 8 ADCs, so 4 clocks (+4 inverted). For Rigol it means when sampling with 1GS/s each of the 100MHz clocks is delayed by 1ns, and for Tekway as well 1ns (but clocks at 125MHz). Sure, this are max values, typical you can get less jitter, but it does not matter for product comparision as both products affected in same way. Sure, Rigol can have total higher jitter, but Tekway can have higher gain drift due ADC overclocking.
So you can see pure from hardware point of view you can have only crap results on both^^ The trick both manufacturer using is to check when after rising edge of ADC 1 ->8 (10) the data is showing zero crossing. These values are then taken to build a skew table to allign the sampled data. But of course the interleave distortion is already in the signal (you can observ on both models that when using single shot a RF wave is more distroted in single shot than when in run mode, for single shot you can't filter out any variation to skew table, for run mode there are some tricks to made signal looking better that it is). The way to work with interleaved ADCs is to measure during calibration the skew (which is different between devices due parts/pcb variance) and to allign all clocks to get same zero cross from all ADCs, but never ever to sample with bad clock and to allign the data afterall. But that's different story. I don't know by 100% who was the first with that idea, from the information about release dates and teardown i would say Instek did it first (and btw, they did it better), then Rigol adapted it into their E models. Short after that others (Tekway/Siglent/ATTEN) adapted it as well. You might find small differences here, like different opamp in S&H on Siglent to reduce the drift on cold DSO, but all these modifications are more or less too small to talk about real differences in signal/trigger integrity.
And yes, firmware A can maybe allign the crap data better than firmware B, as well device A could be better calibrated as deivce B because the technician plugged the cable properly into BNC, and manufacturer A can implement better algos to filter variations as manufacturer B did. But that's are things applied afterall. Knowing hardware on both models, and knowing how they work i know that one can't say "Rigol has excellent signal and trigger integrity" and "Tekway have trigger / jitter issue" at same time. And of course other models using similar/same hardare are affected as well (Siglent/ATTEN).
And once again, there was nothing wrong with Dave's review, he didn't cheated (on purpose'), so yes his statement based on his result is ok. But on the other side i (and other as well) do have working models and i/we know what one can achieve on these DSOs. So there is difference between "Dave's DSO" and "all these DSOs" and all i'm trying to do is to stop people from seeing only "back and white" when there is a rainbow on the sky^^.
I said as well that Tekway/Hantek produced lot of crap in last 3 years (e.g hw1005 disaster or some FPGA design versions), i did said as well that they do firmware issues (sometimes they simply sleeping, like on the long memory in XY trigered mode ... that should be not possible together, but it is and it does produce overflow and dso.exe is crashing^^), but i said as well that they working on it. It is not that the firmware is not sufficient to do most of the work, sure, it is, but there are things like digital filter or equ mode sampling missing/disabled, as well few limitations like zoom in dots mode is not "exact" in last 3 zoom stages. And finally i did said that for a year of so Tekway/Hantek populated very "unfortunate" combination of resistors in frontstage, but this is still within specs on non-hacked DSO but 3-5dB deviations on hacked DSOs - and i did said how this can be fixed (for 8USD).