Ok,
before i edit this response (and add a loooong list of things) let me tell you soemthing Dave, your model is a bit strange. The serial number on the enclosure didn't match the serial number of the mainboard, so someone have already played with that board/DSO.
Hard to say how deep playd and if/what changed (you can e.g. disable the bw filter), but that just a side note.
Let me answer few things here:
-
Long memory (
4k and 40k are working however fast and good, it make as well to enable "50" refresh rate in display menu to speedup a lot knobs response)
is just crap slow. Sure, it can be used for one off things, but to work all the time enabled you would get crazy. The reason is actually simple, they reading the whole 1M from sample buffer (SRAM connected to FPGA and CPLD) into the ARM buffer and working with that data (measurments, what so ever) and displaying that whole waveform. Today this is very uncommon way, normally you would leave the whole data in buffer and read only what necessary to be displayed at once on screen (e.g. 800pts). Btw, the sample buffer is like on Rigol DS1000E in external SRAM, so they filling the stream from FPGA to SRAM already at slower speed (this is why all these DSOs can't do 1GS/s and 1M at time). When you enable the long memory on Rigol, the screen is much faster than on Tekway, already here the difference in data readback is visible (but it should not as both doing the same on hardware level, actually Rigol is even slower here due the non DPO-like buffer). I don't have access to fw sources, but to debug versions, and from what in the code i can see that they working like described, and well, reading the whole buffer only once per second (see init_store_depth functions). This can't be simply changed as the ARM SoC can't just read much more at once. When measuring/looking on the SRAM/CPLD on FPGA (the trigger registers) i can see the DSO running muuuch faster, sure, it is always 4k ring buffer running at full speed. They would have to change the firmware to read only that part what need to be displayed, not the whole buffer.
- Tekway confirmed that wfms/s is up to 2500, like mentioned on their website
http://www.tekway.net/views2.asp?newsid=205&sess=2Hantek told me 2000, but they haven't even edit properly the user manual so who knows
Not that i really trust them both, but i trust my measurment and my eyes. From the code i can see that 40 captured frames will get read at once from sample buffer and that 50 times per second when the screen refresh is set to 50. So 2000 wfms/s max here. The firmware before "merger" with Hantek was much faster (responding), so i assume the 2500wfms/s was measured on that version. When i change the on current version the size of DPO-like buffer all i can get is ~2152 wfms/s is max. So that can be the limit, but of course it can be as well FPGA firmare limit. Anyway, due the fast that the "40 frames to one" buffer can be read back 50 times per second the wfms/s can't be constant, it will be more like burst mode. You can see it on that video i made some time ago (don't get confused, i'm stopping ACQ as soon captured and restarting, so count only the second from restart point to captured on screen^^)
and here compared to TDS700A (doing here 6k wfms/s)
Of course both didn't said anything to question "is the wfms/s conctant or burst mode?", not a real issue as persistency can help here out to let the glitch visible, but it would be better t have constant wfms/s rate.
- there are bugs, as mentioned below i'm helping them out with that. Lot of things fixed since Jan 2013, but not all. Let's hope the best^^. I will not give up that fast, i have a lot of time now.
- there is no intensity grading as know from other DSOs, Tekway/Hantek is using DPO-like grading, 4 steps (each in 4 intensity steps, so 16 steps total in intensity but still only 4 depth, anyway^^). In run mode, with persistency on auto which is the "off" position, the waveform looks like attached picture - same sine waveform captured twice as screen snapshoot (and zoomed on PC to show details). The DPO-like grading is clearly visible (no, this is not a TFT display persistency error, that are captures from memory), however, i would prefer to have here higher depth. Probably FPGA is too small for more. Easier could be to implement only the intensity grading, like Riolg did it on DS1000Z/DS2000, instead of trying to simulate Tektronix. Not that i don't like that idea, as TEK fan i do for sure, but it is not easy to achieve good results at no price. Even TEK didn't managed it in their low-end models.
- the frontend story
For a long time i was fighting with ppl in German forum, i was wondering why they getting crap waveforms on their scopes where my was looking much better. Long story short said - for (unknown to me) reason Tekway/Hantek changed some resistors in their frontend. Btw, this is the same frontend what Rigol is using in DS1000E (that affected part exists even on DS2000). Of course Siglent/ATTEN are using exact the same frontend, hehe. Anyway, i and some other ppl made lot of measurments and simulations, finally we have working combination, it is even better that original DS1000E and even better than my old Tekway. There is no need to change anything on org. DSOs, but on hacked (or all what need to work over 100MHz, this is why this never was an issue on DS1000E). All the necessary information about is in the Tekway hack thread:
https://www.eevblog.com/forum/testgear/hantek-tekway-dso-hack-get-200mhz-bw-for-free/msg212054/#msg212054- jitter, yeah. I actually made measurments (with proper equeipment) and reported the skew between clocks, Tekway almost fixed it (not perfectly but definitely acceptable). Since Nov 2012 they have again new FPGA design (83EB) which seems to be worse than the working one (83E9). The DSO you tested have the 83EB. It seems that very few (i know only 2 by now) current models can't use 83E9, reason seems to be on power rail (smaller caps than before, heh). Some have different DAC installed (on botton side of PCB, so visible from outside), with that DAC 83EB need to be used. For all others is a good idea is to use FPGA design 83E9. Before someone ask "why is 83E9 not perfectly fixed?" Well, don't be naive, Siglent/ATTEN/Rigol C/D/E are clocked by FPGA, and if that not enought with not dedicated clock out pins, this is a worst case 300ns jitter. What all these manufacturer doing is to calculate avg values to middle the results. So far everything ok. However Tekway is having different architecture (DPO-like), so the resulting waveform jumps bit more (as it can be avg and DPO-like together). I worked here with external jitter cleaning chips (thanks again to Silabs for providing me dev boards, lot of samples and lot of help), that solution was working perfectly, but it was too expensive for undr 1k DSO. Honestly i wish Rigol will make lot of presure on other DSO manufactuers with their DS1000Z (they doing it already with DS2000). That will help a lot, the only way to fix such jitter/interleave distortion issues is to use less ADCs and proper clocking, and nobody will spend money without a need. For existing users, well, a very good clock source for FPGA (like CCHD-575) is reducing the jitter as well. More information in the Tekway hack thread.
- i have no idea who is that "smart person", but someone is always trying to cut some parts and save money. I told them this multiple times, it seems they ignoring it and trying it each every few months again. Your review would probably help to fix that. Examples are the forntend (as said above), or some caps near FPGA (they released different FPGA design to fix potential issues, lol), JFET in frontend was changed to crap solution for 3 months or so (they fixed it, but fuck why they did it in first place?), voltage ref is different (still acceptable but it was better one), XO is ±50ppm (but it was for some time ±25ppm, ok datashee talk about 50ppm for timebase so still within specs somehow). I know that the engineer behind the hardware/software is a smart person, all the hidden things in firmware and all the potential extension in hardware are really great, i doubt he is the person reducing costs. Sure, as entrepreneur i know how important is cost reduction, as EE i know there is invisible line which should be not crossed over. Some ppl in china seems to not know that to cut by 1% (with "component savings") works only once and that every month "only 1%" means 12.68% after a year, and thats crap and not quality.
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So let's summarize -
as you said Dave, they almost there, but here and there small and less small things that need to be fixed. Firmware is the "easy" part (if i and they didn't give up), hardware can be only fixed with newer hw revisions (but as said above, others with similar hardware are not better here, that means all Siglent/ATTEN (except the 4channel models), Rigol DS1000E, most UNI-T models), and new models are on the way. No idea how many hw things has been fixed in these Hantek "P" models (with 24k memory only!) and how many will be in new "B" models, but we will soon see it.
I bet all chinese manufacturers (except Rigol, they seems to have good contract with RuiFeng? or AD?) will switch to ADC08D500 as soon they recognize how Instek overclocked these ADCs ^^. That will change the game again.
I'm sure Tekway will learn as well how to achieve higher wfms/s, not that they are bad with 2000 (2500) wfms/s, but Rigol DS1000Z with 30000 and UNI-T with 150000 is complettly different story. Sure, Tekway decided to do it DPO-like, but that was in 2009 and today they can give that up and simply do the "Rigol" (i would say Agilent way here, but i know that Rigol was using that way already in CA models, so before E models has been designed. They simply frozen that idea due costs, E models are working and cheaper).
Anyway, thanks for the review (yes, i know it was not a real review).
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