I believe the formula referencing D/4096 in page 23 is a bit of a datasheet bug... It contradicts Table 4-1 on page 19 which states clearly that 1LSB = Vref /256 * G in the case of the 8-bit part (so for Dave's design that would be 16mV).
So clearly the INL is still tightest for the 12-bit part as one would expect.
Also, agree with @benemorius... The error will be less if only using the gain when it is needed for the full 4.096V range, as with the gain turned off 1LSB on the 12-bit part is .5mV so only +-6mV INL ( or even better by reducing the gain error, which is max 1% of FSR, or 40mV!).