If this AVR had two hardware SPI ports I still would have used two separate hardware SPI ports for this very reason.
It doesn't need two hardware SPI ports because you can share them between multiple devices. Ditto for the I2C port.
Having said that, though, the hardware
does support "USART in SPI Mode" (page 204 of the datasheet). So you effectively have two SPI ports (although the USART one is master only, not that this would matter in your case).
I'm not sure what multiple SPI ports really gives you. Already SPI is pretty fast (eg. about 3 uS per byte, which is around 48 clock cycles). Pretty much as fast as an interrupt can be serviced. So realistically you could only use one SPI port at high speed anyway (by the time you store the data, loop, test if it's time to get another byte and so on).
And it allows the separate DAC/ADC interface to operate on it's own timer interrupt or something similar as well without having to worry about conflicts.
Once you bit-bang, interrupts become more of an issue because
you are handling the timing, not the hardware.
Anyway, thanks for sharing all your design ideas, it's interesting to see how it all comes together.