Getting low noise supply voltages in Systems on Chip type ICs is a difficult issue, many ourselves included opted for distributed regulators throughout the chip rather than try and supply all the circuitry with a single on or off chip regulator.
When we were developing SOTA RF/MW/MMW SoCs many years ago and required very low phase noise on chip frequency references for receive/transmit and clocks, getting close in low phase noise results were obscured by the supply low frequency noise levels which modulated the VCOs in the frequency synthesizers used for various clocks and RF signals. This lead to a development effort for an ultra-low noise fully on-chip LDO which would be stable with any load capacitance, culminating in patent 8692529.
https://patents.justia.com/patent/8692529Recall we achieved a measured noise level of ~12nv/rt Hz for a 2.5V reference which included the bandage reference and scaling amplifier. The LDO was a somewhat unique architecture to allow low noise, stable transient response, and achieve overall stability with any load capacitance.
Much later while at a IEEE ISSCC conference a young intel engineer presented a almost identical regulator that was employed in the latest processors, this regulator was used in on-chip clock distribution for filtering for the various VCOs. Had a nice discussion with the author and showed how they could significantly improve the low frequency noise with the addition of a single pinch resistor/fet.
Anyway, I've found during my career that low noise high DR designers typically don't consider the regulators and supply rails until the end of the design cycle rather than much earlier, and likely only after extensive lab measurements which were eventually traced to the regulators
Best,