EEVblog #1353 - WHY Are These Pins Shorted?

[EEVblog]

Eagle eyed viewers spotted a short between two pins on a TQFP chip in the previous teardown video. This isn't a dodgy assembly issue, it's a deliberate design short, Dave explains how and why.
Solder masks and snap grids.

[free_electron]

That would be grounds for immediate dismissal of the pcb designer ... NOT done. As Dave said AOI has trouble with this. The same goes for shorting two adjacent (non power) pins underneath a package. if later on that bridge needs cutting it is a nightmare to access. Links should be accessible. Same goes for flooding planes across power pins. You cannot run a trace that is wider than the pad across the pad. It is illogical to begin with. The electrons follow the shortest path anyway. They don't go into 'dead space'.

Now, on a second note : the footprint shown in the video is a total disaster ! There is too much toe area and virtually no heel area. The strength of a gull wing bond is in the heel area . The toe of a RoHs gullwing pin isn't even wettable. The leadframe alloy does not bond to warm tin. you can deposit it chemically though. But, when the component is sheared out of the leadframe the tips are cut. So the vertical portion of a pin is bare alloy that is not plated and thus unsolderable. if you have no heel area you depend purely on the bottom of the pin to top of the board contact and that is very weak mechanically speaking.
There is no 'sideways' heel as the pads can be the width of the pin without overlap ( you actually don't want to make pads wider than the pins for two reasons : 1) self alignment during reflow if there is wiggle room the part may sit 'crooked' 2) maximisation of soldermask sliver. Any extra copper there pushes back the soldermask opening ). The best mechanical retention is formed in the heel of the pin to pad. You will get a nice solder fillet there that flows up the backslope of the gullwing pin.

[Unixon]

This is exactly why I hate this kind of shorts and restrict EDA from making them - it is hard to tell if a particular short is designed in or not and figuring this out over and over is a complete waste of time.

[T3sl4co1l]

Now, on a second note : the footprint shown in the video is a total disaster ! There is too much toe area and virtually no heel area. The strength of a gull wing bond is in the heel area . The toe of a RoHs gullwing pin isn't even wettable. The leadframe alloy does not bond to warm tin. you can deposit it chemically though. But, when the component is sheared out of the leadframe the tips are cut. So the vertical portion of a pin is bare alloy that is not plated and thus unsolderable.

The DFM guys I talk to, say that as long as at least one fillet is present, the other doesn't matter too much.

For some reason they haven't mentioned non-wettable areas though; and I've definitely seen that on real parts!

if you have no heel area you depend purely on the bottom of the pin to top of the board contact and that is very weak mechanically speaking.
There is no 'sideways' heel as the pads can be the width of the pin without overlap ( you actually don't want to make pads wider than the pins for two reasons : 1) self alignment during reflow if there is wiggle room the part may sit 'crooked' 2) maximisation of soldermask sliver. Any extra copper there pushes back the soldermask opening ). The best mechanical retention is formed in the heel of the pin to pad. You will get a nice solder fillet there that flows up the backslope of the gullwing pin.

Indeed, IPC for example says side fillet can be -0.02mm.  I find good success with e.g. 0.5mm pitch and 0.23mm width pad, which leaves just enough at 0.076mm mask expansion to meet a 0.1mm sliver limit.

(And yes, the DFM guys don't like the between-pad traces either!)

Tim

[BrianHG]

Now, on a second note : the footprint shown in the video is a total disaster ! There is too much toe area and virtually no heel area.........

This is typical of Protel's disastrous QFP footprint generator of the time and their default footprints.
Also, the lousy datasheets of the time and the way they defined the package dimensions.

At the time, I wrote my own footprint generator for Protel in their built in scripting language which used actual measurements from the datasheets and it calculated the toe area and area underneath the pad necessary for good manufacturing while working out where the pad's new center would be.  This resolved damn calculation errors which can happen when doing this by hand.

[free_electron]

The DFM guys I talk to, say that as long as at least one fillet is present, the other doesn't matter too much.

NASA did vibration studies and stress testing and the heel fillet is much more stronger than the toe fillet.
i'll find the document and post thelink.

-snip- For some reason they haven't mentioned non-wettable areas though
-snip- IPC for example says

IPC is nothing but a self-aggrandizing money making machine. I have come to distrust and despise them.
Their standards are no standards....only 'guidelines'. 10 year out of date...
A lot of it is vague hand waving and a lot of wording is 'it depends' and not rooted in real life. Their current handling curves and formulas used for 50 years by almost everyone are proven to be totally bogus and completely wrong !
Their committees are islands of power that don't talk to each other. I have had heated discussions with them . Here's a real stinker : 7351 defines toe and heel space. You need a pad with x and y for to and heel. Then you read their assembly specs ( 600 series) and all of a sudden it is OK if the toe of a pin hangs over the edge of the pad . What the fuck are these people drinking ? You need to design it so the pin is shorter than the pad, but when you assemble it , it is ok that the pin hangs over ... answer from IPC reps : the layout and manufacturing are different comittees and they don't always talk to each other . And those are the people that want to sell you their "standards" ? There aren't enough facepalm icons in the world...
note: and if you raise the non wettable toe of rohs parts they go blank.. oh we haven't gotten around to updating that bit yet ... what? 15 years after RohS became effective ?

go read and cry your eyes out :

https://www.signalintegrityjournal.com/articles/1406-pcb-trace-currenttemperature-relationships-and-their-dependencies
https://www.circuitnet.com/experts/87862.html
https://www.circuitnet.com/experts/86635.html
https://passive-components.eu/smt-electrolytic-capacitor-solder-joint-criteria-and-integrity-investigation/
https://ieeexplore.ieee.org/document/76120
https://apps.dtic.mil/dtic/tr/fulltext/u2/a267598.pdf
https://www.ti.com/lit/slua271

[VK3DRB]

The PCB designer was not very good. He may have been lazy, inexperienced, or under too much time pressure to to do the job properly. Manufacturing staff, technicians and whoever might see this as an undesired solder short. There is no reason he could not have moved this off to the mask area as Dave points out.

The designer's designator standards are a bit bizarre. MIC1 for U1? MR23 for R23? Not very efficient, not very logical and not standard. MIC is more logically for microphone, not an MPU. His MPU pin 1 marker is complete garbage (like playing Where's Wally). Also notice no teardrops, no tented vias etc. The PCB is certainly not artwork.

His "RS232" and "RX" texts overlap each other unnecessarily. Also the "TP3" with an arrow overlaps the another line co-linearly. Design rules can weed crap like that out. At least he used arrows for distant test points. Who knows what ambiguities there are with his designator placement on the board. Leaving designators out because it appears there is no room is generally bad practice. One can use call-outs to handle a tight group of components, like 0402 or 0201 R's and C's in a cluster.

On high density boards, I always aim for 100% net test point coverage (except of course for things like UHF RF transmission lines!). There is no need to "TP" to be used, because there is no other component designator standard having just a number. So for test points, if there is a lack of room, omit the "TP" everywhere and use a number. Altium handles the test point as a number perfectly as a component. For example "3" would replace "TP3". It works when you don't have much room for text. Incidentally, these days, with a reasonable PCB manufacturer, your text can go down to 0.6mm high, 0.12mm stroke width if necessary as the exception rather than the rule (ie:5:1 ratio) for decent readability. I generally go for 0.8mm/0.16mm on high density boards as standard.

[VK3DRB]

IPC is nothing but a self-aggrandizing money making machine. I have come to distrust and despise them.
Their standards are no standards....only 'guidelines'.

I once worked for a company not too long ago where the QA manager enforced IPC standards on everything and he would inspect and fail anything that did not meet them. Even so, most of the IPC standards are common sense but sometimes are inappropriate. The IPC raw PCB (eg: bow and twist) and PBCA soldering standards are useful and can be listed in a PCB design as a requirement. Then you have something to go by when the soldering is crap and the board is excessively bowed, for example.

IPC are not such a money making machine. A nasty one is Bluetooth.com. Hand over $US 8K for EACH product you design that uses Bluetooth, else you risk getting a letter of demand for money or being taken to court by them and sued. That includes if you use a use an already approved compliant Bluetooth module inside your product. Their fees are punitive for small businesses and startups.  https://www.bluetooth.com/develop-with-bluetooth/qualification-listing/qualification-listing-fees/.

[T3sl4co1l]

I sometimes put net names instead of test point designators -- if I'm being nice and have room.  Or put them on a separate [mechanical] sheet (labels, and markers), very handy for proto debugging!

Tim

[Poe]

The board house themselves (not the designer) most likely eliminated the mask between the pads in order to eliminate the narrow mask SLIVERS (not slithers).  You can tell by the straight mask edges.
If it was the board designer, there would likely be a scalloped mask edge.

Only the more expensive board houses actually notify their customers when the gerbers are changed.  It's not uncommon at all for gerbers to be 'tweaked'.

Dave, please at least do at least a little video editing.  I and many others enjoy the vids but can't justify spending 23minutes on 1minute worth of content.

For example, the following took two minutes to write and one minute to read:
     Some people thought this was a solder short.  It's actually a solder covered trace.  I can tell that because the trace is in the middle of the pads, where the design software would snap to.

     Ideally you want mask between the pads, but in this case the pads are too close for the PCB manufacturer's capabilities.  Some people might be surprised by PCB manufacturer's actual capabilities regarding mask expansions and slivers.  Lets look at JLCPCBs:

     Traces between pads like this are not good because visual inspection might waste time when they assume it's a short.

[f4eru]

Please, guys, take the habit to do it properly.
That saves grey hair for manufacturing people.

An example how to do it correctly :

[free_electron]

Please, guys, take the habit to do it properly.
That saves grey hair for manufacturing people.

An example how to do it correctly :

close ,, your via entry is acute. teardrop it

[Zucca]

https://electronics.stackexchange.com/questions/13205/why-are-there-teardrops-on-pcb-pads

[free_electron]

https://electronics.stackexchange.com/questions/13205/why-are-there-teardrops-on-pcb-pads

the main reason for teardrops are
1)  to avoid failures due to drill 'wander' in parts with small annular rings. if you have an annular ring that i larger than half the drill size there is no need for teardropping. unless ...
2)  to avoid mechanical stress from tearing of the track. hairline cracks form the most easy on the track/pad junction. if you leave a large pad with a tiny trace that i a weak spot. teardropping mechanically strengthens that location.