Hi,
we now have support for PFC232. A flash based "Multi-Core" IC (in development branch).
I added a dual core example hello world:
* core 1 sends out the "Hello World!" string
* core 2 detects pin changes on incoming serial port and sets a flag
* when core1 sees the flag it will clear it and output a '2' (hello from core 2)
When you run the 2core hello world directly in easy pdk programmer it will capture and output the "Hello World!" and when you press a key on the host computer (which causes serial data to be sent, which causes pin changes detected by core2) you will get some '2' outputs:
./easypdkprog -n PFC232 write Examples/src/build/helloworld_2cores_pfc232.ihx -v
Searching programmer... found: /dev/tty.usbmodem1234567855AA1
FREE-PDK EASY PROG - HW:1.2 SW:1.3 PROTO:1.4 (1.3-40-g98c7c8d-dirty)
HWVAR:0 HWMOD:1
Erasing IC... done.
Blank check IC... done.
Writing IC (321 words)... done.
Verifiying IC... done.
Calibrating IC
* IHRC SYSCLK=8000000Hz @ 5.00V ... calibration result: 7949466Hz (0x70) done.
./easypdkprog start
Running IC (5.00V)... IC started, press [Esc] to stop.
Connected @168421 baud
Press a key on the host computer to send some bits, core2 will detect this and core1 will output a '2' for every 1 bit
Hello World!
Hello World!
222222222222222222Hello World!
222222222222222222222Hello World!
Hello World!
IC stopped==> BE AWARE: SDCC PDK compiler does not support code generation for parallel execution of functions. Our best chance is to use SDCC C code for core1 and write assembly code for all additional cores.
JS
P.S. Calibration seems a bit wrong. That's why it shows so high baud rate. I will have look at it.
Edit: Interesting... The 7 cycle calibration loop seems to take 10 cycles on this IC.
Where are the 3 extra cycles coming from ? ? ? The IC runs in "single core" mode during calibration.
Calibration loop is like this:
LOOP:
SET1 IO(0x10).3 (PA.3)
MOV IO(0x0B), A (IHRCR)
T0SN IO(0x10).4 (PA.4)
ADD A, 0x01
SET0 IO(0x10).3
GOTO LOOP
Maybe it is from context switching between cores, even that FPPEN only activated core 1 during calibration?
When setting the fuse bit to use only 1 core then the above loop will take the exact 7 cycles.
Looks like PDK IDE + WRITER also sets the (single core) fuse before calibration. I wonder what this fuse actually means...
EDIT2: During analyzing the PDK IDE stub inserted for PFC232 IC calibration I found 2 new undocumented instructions in 14 bit instructions set.
Most likely LDTABL and LDTABH
(like in 15 bit instruction set).
0 0 0 0 0 1 0 (7-bit MEM addr) 0 LDTABL M : A ← LowByte@CodeMem(M) (last bit of M set to 0, M must be word aligned)
0 0 0 0 0 1 0 (7-bit MEM addr) 1 LDTABH M : A ← HighByte@CodeMem(M) (last bit of M set to 1, M must be word aligned)
Very useful for lookup tables in code mem...