EEVblog #1081 - Are Bypass Capacitors REALLY needed?

[David Hess]

(although I've seen schematics where the capacitors are all shown in a array block on a page, and the designer placed them that way on the board).

Better to laugh than to cry at such things...

I reserve crying for when purchasing and management replace the parallel capacitors shown in the schematic with a single expensive non-standard value of the same total size.

Some schematics have a separate page showing power distribution to the various circuits and packages along with the associated decoupling capacitors.

[ignator]

Quote from: T3sl4co1l on Today at 01:34:13 am

FWIW, not the best plan: power planes are better capacitors than the components are!

Indeed, bypassing planes, one needs to be careful that the bypasses themselves don't make things worse.  A plane is typically a few nF (obviously, depends on size and thickness) of nearly-ideal capacitance, with a modest Q at most frequencies (>20?), and every connection to it incurs at least a few nH because of via and body length.  So, of course -- use the same analysis as ever: check R, L and C and make sure it's dampened!

Tim

Yes, I agree about board capacitance being much better then bulk capacitors, but the bulk caps provided the large charge transfer energy, and the board cap provided the high frequency decoupling.
We did have a few  designs that had resonance problems, where parallel capacitors intrinsic inductance made a tank circuit. Made a real head scratcher when the emission plot got worse when doing the emission corrections.
There was a design from the airdata computer that had a clever special board capacitor layed out for each component. The EE called it the "Island of Quiet". This was isolated from the power plane directly under the part, and then stitched in the large charge source capacitors around the edge of this Island. The island was connected to the power plane with only one controlled connection, the intent to create a small inductor. His problem was keeping the processor noise out of the A/D converter. You can lift their pressure transducer a few inches off the bench, and see LSBs counting up, and absolutely no LSB jumping about. This also enabled compliance to radiated HIRF of 200-600V/m over the frequency range (memory 1MHz to 16GHz).

[EEVblog]

Quote from: T3sl4co1l on Today at 01:34:13 am

FWIW, not the best plan: power planes are better capacitors than the components are!

Indeed, bypassing planes, one needs to be careful that the bypasses themselves don't make things worse.  A plane is typically a few nF (obviously, depends on size and thickness) of nearly-ideal capacitance, with a modest Q at most frequencies (>20?), and every connection to it incurs at least a few nH because of via and body length.  So, of course -- use the same analysis as ever: check R, L and C and make sure it's dampened!

Tim

Yes, I agree about board capacitance being much better then bulk capacitors, but the bulk caps provided the large charge transfer energy, and the board cap provided the high frequency decoupling.
We did have a few  designs that had resonance problems, where parallel capacitors intrinsic inductance made a tank circuit. Made a real head scratcher when the emission plot got worse when doing the emission corrections.
There was a design from the airdata computer that had a clever special board capacitor layed out for each component. The EE called it the "Island of Quiet". This was isolated from the power plane directly under the part, and then stitched in the large charge source capacitors around the edge of this Island. The island was connected to the power plane with only one controlled connection, the intent to create a small inductor. His problem was keeping the processor noise out of the A/D converter. You can lift their pressure transducer a few inches off the bench, and see LSBs counting up, and absolutely no LSB jumping about. This also enabled compliance to radiated HIRF of 200-600V/m over the frequency range (memory 1MHz to 16GHz).

I included links in my original post to IBM research on power plane capacitance and adding distributed bypass caps, screen cap was in the video. Very interesting stuff.

[EEVblog]

One other note: At 30:50 in the video you mentioned these were "real little things happening in the circuit".  I'll assume you know exactly why your getting the knee in the signal. That is the transmission line and the knee in the signal is telling you you probed closer to the source side of the transmission line as opposed to the destination. Surely you recall your t-line fundamentals from school?

Of course, and that's was what I was alluding to. Those reflections are present in the circuit at the probed point, that's actually happening to the signal on the board at that point, it's not the probe causing that.
I wasn't going to go down that rabbit hole, the video was already way longer than I wanted it to be.

[engineer_in_shorts]

Think about the time period of muntzing and tube TV sets.  The only way to construct circuits was hand build circuit point-to-point, there maaaaaay have been PCB.  But anyway point-to-point or PCB, the cost saving of removing a part was not just the component but also the construction cost.

These days automated SMT is accessible for even very small volume batches of PCB builds, so if you need to put one part (e.g 100nf) there is almost zero cost to 10 more.  At least for passives.

Is bypass caps even a big part of 1950s tube TV set construction? I suspect there are also other parts that can be removed but without side cutters.  For example resistors to soften start-up currents.

[KE5FX]

Think about the time period of muntzing and tube TV sets.  The only way to construct circuits was hand build circuit point-to-point, there maaaaaay have been PCB.  But anyway point-to-point or PCB, the cost saving of removing a part was not just the component but also the construction cost.

These days automated SMT is accessible for even very small volume batches of PCB builds, so if you need to put one part (e.g 100nf) there is almost zero cost to 10 more.  At least for passives.

Is bypass caps even a big part of 1950s tube TV set construction?

Sure.  If you have a ton of gain, maybe as many as four or five consecutive IF stages, you'd better have a ton of decoupling, or your B+ bus will turn into a feedback path. 

But do you need bypass caps on every screen grid?  Wellllll.... no, probably not. 

It's really the exact same question.  Remember, as far as the business world is concerned, engineering is the art of building a bridge that will barely stand up, a TV that works most of the time, a car that will fail 6 days after its warranty expires, or a computer that needs constant babysitting by expensive service personnel in natty blue suits. 

[f4eru]

That was an interesting experiment !
A few remarks though :
- Dave should have looked at the 5V line with the scope input in AC coupling
- Linear Regulators can often get unstable when removing the bypassing, especially modern ones, so you could have a crash not due to signal integrity
- some ICs fom that era have internal bypass caps, bonded directly to the side of the die. A ceramic packaged 6502 I openned recently had one.
https://psearch.en.murata.com/capacitor/lineup/gma/
- modern fast ICs are much much worse from the current hits banging on the supply lines, and from the smaller noise margin of the logic levels.

[temperance]

Hello,

@14:32
there is no problem. The bus is being pulled up because nothing is driving the bus and the next value on the bus is clearly a zero. It's less visible if the next value is a one. Nu bypass cap will change that.

@31:00:
Nothing special here. WHat you see is a transmission line being driven. The flat portion in that signal indicates that the device being driven is changing it's state. It's actually sloping a little down because the driver output resistance is changing while the bus is being driven. Bypass capacitors aren't going to help you. Cooling the board will make this transitions more flat. The "unstable" high signals will improve too when the board is cooled. But they are stable enough to not cause any problems. It's the GND which requires attention because the noise margin is much lower for zero's. And that's also why TTL level IC's use active low chip selects. For CMOS levels it doesn't matter because the noise margin is symmetric.
 

Perhaps you can try an AM radio next to board while removing the capacitors one by one. Maybe you'll be able to hear the difference.



Regards

[free_electron]

Of course you can design without requiring bypass caps.
the Cray -1 had nearly no bypass caps. and that thing is enormous. the design used carefully balanced differential signalling that caused no dynamic load on the power rail ( when one pathway went from 0-1 another went from 1 to 0 so the total current consumption was quasi-static) The voltage rails had virtually no ripple as they used rotary converters to make 400Hz AC that was then rectified. There is very little amplitude ripple on a 400hz rectified supply with a constant load.

another common mistake these days is 'sprinkling' 100nf caps. 100nf worked as long as the clock does not go above roughly 50 MHz , once you start switching faster than that a 100nF doesn't do a whole lot anymore and you need to drop to 10nF and below.

It is all about handling dynamic load transients. if you have a bunch of logic all banging away at the same time your supply sees tremendous load changes. That's why complex systems use clock dithering and spread spectrum. It avoids massive load jumps.
It is VERY hard to make a power supply that can cope with fast transients. AN old quadcore pentium could go from a few ampere to 80 ampere in a few microseconds. that made power supplies hell to design.
Now they use special regulators on-board that communicate with the core. The core knows when it will bang the supply and they stage the regulators in sync with the core operations.
To give you an idea : A processor for tablets talks to its power chip at an update rate of 3 million ops... just to regulate the 1.2 volt core supply rail. the core lets the regulator know if it is going to increase or decrease consumption

[KE5FX]

Of course you can design without requiring bypass caps.
the Cray -1 had nearly no bypass caps. and that thing is enormous. the design used carefully balanced differential signalling that caused no dynamic load on the power rail ( when one pathway went from 0-1 another went from 1 to 0 so the total current consumption was quasi-static) The voltage rails had virtually no ripple as they used rotary converters to make 400Hz AC that was then rectified. There is very little amplitude ripple on a 400hz rectified supply with a constant load.

Absolutely.  Everybody who does this stuff needs to take a few hours during their next pilgrimage to the Bay Area and check out the Crays exhibited at the Computer History Museum in Mountain View.  That style of wiring is useful to hundreds of MHz, they didn't even push it to its limits.

another common mistake these days is 'sprinkling' 100nf caps. 100nf worked as long as the clock does not go above roughly 50 MHz , once you start switching faster than that a 100nF doesn't do a whole lot anymore and you need to drop to 10nF and below.

That, not so much.  100 nf is actually a good minimum value for bypassing in many cases.  Textbooks may say one thing, but actual measurements will show that smaller values are often of minimal benefit, and can actually make matters worse.  See the link in my post earlier in the thread.

The thing about a large-value ceramic cap is that electrically, it looks like a whole lot of smaller ones in parallel.  Use large value caps in small packages and you can ignore most of the scary stories out there.

[T3sl4co1l]

The thing about a large-value ceramic cap is that electrically, it looks like a whole lot of smaller ones in parallel.  Use large value caps in small packages and you can ignore most of the scary stories out there.

Exactly, the impedance of a 10uF cap in 0603 is identical to the impedance of a 10nF 0603, above 50MHz (in the ESL asymptote).

Tim

[free_electron]

The thing about a large-value ceramic cap is that electrically, it looks like a whole lot of smaller ones in parallel.  Use large value caps in small packages and you can ignore most of the scary stories out there.

Not true ! as the frequency increases the plates furthest away from the pcb perform less and less.

An mlcc is indeed a stack of plates much like a stack of paper sheets. For very high frequency ripple , such as found in very fast processor cores ( >1GHz clockspeed ) the sheets at the bottom have a shorter electrical length than the plates at the top.

That is why we have structures such as vertical caps ( where the plates are vertical as opposed to horizontal. don't flip the part 90 degrees ! it is the same part but during taping they make sure the parts sits with the plates vertical. this can be ordered from certain vendors like samsung) and things like X2Y caps

http://speedingedge.com/PDF-Files/X2Y%20vs%200402%20081605.pdf

in an X2Y cap the current is forced THROUGH the capacitor. http://www.x2y.com/bypass.htm
This requires proper PCB layout. Simply flooding planes does not work with X2Y caps. power goes in one pin and comes out the other pin. These things are 4 terminal devices

once you start dealing with fast transients such as found in multicore processors , big FPGA's and GPU's you can't escape such things anymore. there is very little margin on a 0.9 volt main rail...

[T3sl4co1l]

Not true ! as the frequency increases the plates furthest away from the pcb perform less and less.

An mlcc is indeed a stack of plates much like a stack of paper sheets. For very high frequency ripple , such as found in very fast processor cores ( >1GHz clockspeed ) the sheets at the bottom have a shorter electrical length than the plates at the top.

More importantly, the end caps shield the inside and further-away surfaces, due to skin effect.  Skin effect still applies, whether that current is flowing in a dielectric or not!*

(*It wouldn't, actually, not in an ideal dielectric.  But barium titanate is hardly an ideal dielectric: it's quite lossy even at modest frequencies, giving rise to skin effect in the same way that metal resistivity does.  The skin depth will be different, of course.)

Fortunately, the plates at the top aren't contributing anything, since we're talking frequencies where the capacitive reactance has long since saturated compared to circuit impedance (i.e., over a few MHz for large values).  So the RF path length and impedance only continues to drop (until such point where ESL takes over, of course).

That is why we have structures such as vertical caps ( where the plates are vertical as opposed to horizontal. don't flip the part 90 degrees ! it is the same part but during taping they make sure the parts sits with the plates vertical. this can be ordered from certain vendors like samsung) and things like X2Y caps

http://speedingedge.com/PDF-Files/X2Y%20vs%200402%20081605.pdf

in an X2Y cap the current is forced THROUGH the capacitor. http://www.x2y.com/bypass.htm
This requires proper PCB layout. Simply flooding planes does not work with X2Y caps. power goes in one pin and comes out the other pin. These things are 4 terminal devices

Although that's how they show them used, flooding planes...

On that note, there was the Proadlizer filter/caps they used on the PS3,
https://www.nec.com/en/global/techrep/journal/g06/n05/pdf/t060514.pdf
but it seems they didn't catch on, and soon went out of stock as that generation of game consoles ceased production.

once you start dealing with fast transients such as found in multicore processors , big FPGA's and GPU's you can't escape such things anymore. there is very little margin on a 0.9 volt main rail...

Their (X2Y's) documentation is wholly unconvincing, and the single source, plus increased cost, seals the deal: you can do much better on all fronts with two or more 0402s or 0603s.

Or conventional cap arrays, if you like -- alternating +/- along each side of a quad 1206 will do better still!

Tim

[free_electron]

Their (X2Y's) documentation is wholly unconvincing, and the single source, plus increased cost, seals the deal: you can do much better on all fronts with two or more 0402s or 0603s.

Or conventional cap arrays, if you like -- alternating +/- along each side of a quad 1206 will do better still!

Tim

They don't really cost much more and you can get away with one or two as opposed to 40 dust caps. very important to shove them under a 1500 pin BGA ...

For really advanced stuff : embedded capacitor foil in the PCB. The prepreg between power and gnd planes is replaced by a capacitor foil. Works wonders !
and for really tricky stuff : simply embed passives inside the PCB. Cavities are milled inside the board and conventional ceramic caps are bonded using thermoset conductive paste. you don't see the components form the outside. This is used to embed bulk capacitance (>1uF) you can't do with the capacitive foil. Sprinkle 2u2 or 4u7 4v 0201 directly under the regulator pads.

[T3sl4co1l]

They don't really cost much more and you can get away with one or two as opposed to 40 dust caps. very important to shove them under a 1500 pin BGA ...

One or two?!  You'll excuse me if I shout bullshit without the eye diagrams to back that up.

For really advanced stuff : embedded capacitor foil in the PCB. The prepreg between power and gnd planes is replaced by a capacitor foil. Works wonders !
and for really tricky stuff : simply embed passives inside the PCB. Cavities are milled inside the board and conventional ceramic caps are bonded using thermoset conductive paste. you don't see the components form the outside. This is used to embed bulk capacitance (>1uF) you can't do with the capacitive foil. Sprinkle 2u2 or 4u7 4v 0201 directly under the regulator pads.

You cost-no-object boys get to have all the fun.  Sigh...

Tim

[KE5FX]

The thing about a large-value ceramic cap is that electrically, it looks like a whole lot of smaller ones in parallel.  Use large value caps in small packages and you can ignore most of the scary stories out there.

Not true ! as the frequency increases the plates furthest away from the pcb perform less and less.

Make some measurements, and get back to us.

Hint: measurements made by people selling fancy capacitors tend to look different from the ones you make yourself.  Only the audiophiles have a keener sense of marketing than those folks do.

E.g., let's see some plots of 0402s versus 0306s.  I have some of the latter around here, but haven't had time to poke at them yet.

[free_electron]

They don't really cost much more and you can get away with one or two as opposed to 40 dust caps. very important to shove them under a 1500 pin BGA ...

One or two?!  You'll excuse me if I shout bullshit without the eye diagrams to back that up.

For really advanced stuff : embedded capacitor foil in the PCB. The prepreg between power and gnd planes is replaced by a capacitor foil. Works wonders !
and for really tricky stuff : simply embed passives inside the PCB. Cavities are milled inside the board and conventional ceramic caps are bonded using thermoset conductive paste. you don't see the components form the outside. This is used to embed bulk capacitance (>1uF) you can't do with the capacitive foil. Sprinkle 2u2 or 4u7 4v 0201 directly under the regulator pads.

You cost-no-object boys get to have all the fun.  Sigh...

Tim

embedded capacitance foil is cheaper than all the loose parts + assembly time. it saves board real estate, reduces routing complexity and the end product is cheaper.

[srce]

One other note: At 30:50 in the video you mentioned these were "real little things happening in the circuit".  I'll assume you know exactly why your getting the knee in the signal. That is the transmission line and the knee in the signal is telling you you probed closer to the source side of the transmission line as opposed to the destination. Surely you recall your t-line fundamentals from school?

Of course, and that's was what I was alluding to. Those reflections are present in the circuit at the probed point, that's actually happening to the signal on the board at that point, it's not the probe causing that.
I wasn't going to go down that rabbit hole, the video was already way longer than I wanted it to be.

Alas, I didn't learn about t-lines at school, but did come across this myself a couple of weeks ago.. I wrote the following for another forum, which may be of interest to some. 

I was looking at similarly distorted waveform on the output of a 22.5MHz oscillator on a PCB I'd knocked up:



Here's a photo showing the oscillator and the traces to the ICs it fans out to and where on the header, close to the oscillator, I was probing.



Thinking that at just 22.5MHz, it's a relatively low frequency signal, I didn't pay too much attention to its routing. I was more interested in having modular PCBs so I could experiment with different parts. These are pretty small PCBs, so the total distance from the oscillator output pin, through the header and to the furthest input pin on the AND gate IC is just 35mm. That didn't seem too far.

Alas, my intuition is often wrong. So let's sim it. To begin with, we need to understand the geometry of the PCB and the trace. This is a two layer PCB, with a ground plane at the bottom and the signal trace on the top - a microstrip. Here's a cross section:



The propagation speed of an electrical signal through a top-layer PCB microstrip, can be calculated with:



Here, c is the speed of light, and Er is the relative permittivity (or dielectric constant) of the PCB substrate. For this PCB, I'm using FR-4 material for the substrate, so this value is around 4.5. The scaling of Er by 0.475 and adding 0.67, accounts for the fact that the FR-4 substrate is only below the microstrip and we have air above. If this were a four layer PCB and our microstrip was on one of the inner layers, we'd need a different formula.

Code: [Select]

er=4.5; % relative permittivity of dielectric for FR4
eeff = 0.475*er+0.67; % effective permittivity for top layer microstrip (substrate material is only on one side)
c=3e8; % speed of light
vp_mps=c/sqrt(eeff); % speed in m/s
vp_mmpns=1e3*vp_mps*1e-9 % speed in mm/ns
tpd=1000/vp_mmpns % propagation delay in ps/mm

So in 1ns, a signal will travel around 180mm. This means it takes 35/180=195ps for a signal to travel from the oscillator to the AND gate IC. 

If the clock were a 22.5MHz sine wave, then its rise time would be 1/22.5e6/2=22ns. However, it is actually closer to a square wave with a rise time of 600ps, so approximately .35/.6 = 600MHz bandwidth. In the former case, the rise time is much greater (112x) than the propagation delay, in the latter, it's fairly close (3x). Let's run a spice sim to see why this relative difference is important.

In order to tell our spice simulator how to simulate this, we need to create a transmission line model, based on the above microstrip geometry:

Code: [Select]

.model top_trace u level=3 plev=1 elev=1 nl=1
+ th=1.378mil ht=63mil kd=4.5 dlev=1
+ wd=12mil
.end

We can then create a schematic in spice that consists of a voltage source, followed by the transmission line model, and then a 4pF capacitor to simulate the input pin capacitance of the IC at the end of microstrip. I've split the transmission line model in to 8 equal parts, so we can probe at different points to see what is going on along the line.



Rather than immediately trying to model the oscillator's actual output and real trace length, we can start with a simplified example. We can look at how a single 600MHz sine wave pulse (the highest frequency component in the square wave) would propagate down an 800mm microstrip (a very big PCB!).



We can see the voltages at different points along the line in the top 8 waveforms, with the bottom 8 waveforms showing the current at the same points. We can see that because we have a capacitor at the end of the microstrip, the pulse is reflected back. When the reflection initially occurs, we can see the current reverse direction (it becomes negative), then we can see it lead voltage. The simulated round trip time is around 9.6ns. The speed was therefore 2*800mm/9.6n = 167mm/ns, which is close to the estimated value above (The formulas used by spice will be more accurate than the approximation above).

If we decrease the length of the microstrip to 400mm, we can see that the wave is reflected back sooner, as it has less distance to travel.



If we decrease the length again to 80mm (so that the round trip time is 2*80/167=0.95ns), we can see the reflected pulse is constructively interfering with the initial pulse. The pulse shape observed depends upon where exactly along the trace you probe:



If we reduce the length to 8mm (with a roundtrip time of 2*8/167=95ps), the reflections are so fast, that they don't distort the waveform:



So we can see that if the round trip time is greater than about 1/6th of the rise time, the reflections are going to distort what we see with a probe. And the distortion observed will depend where along the trace we probe.

We can then change the voltage source in the schematic to create a square wave closer to what the oscillator outputs, to see if we can see something similar as was seen with the real oscilloscope, in order to validate our model.



And that looks pretty similar. If we then shorten the microstrip length, the distortion disappears.

So, as most probably already knew, we need to start worrying about reflections when the round trip time is greater than about 1/8th of rise time and keep the traces as short as possible. 

[Phoenix]

I thought I'd share my latest EMC radiated emissions results from a 7? year old product Ive inherited and doing a 3G -> LTE upgrade on. The main microcontroller (4.912MHz) had insufficient decoupling capacitors causing it to fail radiated emissions. The oscilloscope also showed about 60mVp-p of high frequency ring on the 3.3V rail near the uC.

Red/Green - Original electronics, insufficient decoupling, not sure how this even passed, probably subtle changes in manufacturing. Note the high power narrow band spikes that are at harmonics of the main uC clock. If you look at peak 1 in red the quasi-peak is basically the same as the peak indicating the noise is also constant.
Blue - With proper decoupling near each IC power pin. No narrowband spikes, now passes CISPR32 with about 5dB margin.

Are bypass capacitors really required? Yes.