EEVblog #1081 - Are Bypass Capacitors REALLY needed?

[EEVblog]

Can a product work without ANY bypass capacitors?
Dave finds out by "Muntzing" the Gigatron TTL computer.
Lots of talk on bypassing, grounding, probing, signal fidelity, ground loops and noise and crosstalk.

[rs20]

Very interesting video, really enjoyed it! However, I have to say that the glitches at 14:38 are being blown out of proportion a bit.

I'm sure you're aware that output signals from complex asynchronous circuits (sometime even single ICs) can flip-flop more than once in response to a change to an input due to that input signal branching out and then recombining with various different delays inside the circuit. The classic example being an AND gate and an inverter set up to output A & (!A). Although that circuit is obviously always supposed to output False/0V, it can end up outputting a brief glitch/runt pulse on the rising edge on A because the inverter has a little delay, so it briefly outputs newA & (!oldA). Asynchronous adders (like e.g. 74HC283) are a classic source of this "issue".

So with that in mind, I think it's inaccurate to say that any runt pulses you see are "obviously caused by grounding issues". Because even though grounding issues or decoupling can create or worsen this phenomenon, this phenomenon can occur in theoretically perfectly well-grounded and decoupled systems.

It's also an omission to make it sound like this phenomenon is a definite sign of a problem that must be fixed. The nasty edge at 16:25 is almost certainly not intentional. However, it's probably not a problem at all because a subsequent part of the circuit will be latched. As long your signal finishes its BS wiggles or "second bites of the cherry" before a subsequent latch samples the signal, those wiggles are perfectly inconsequential (aside from wasting power and worsening emissions).

More specifically, it would be a real shame if a newbie saw runt pulses in their own circuit and then concluded that they should add decoupling caps until the runt pulses go away, when not only might decoupling caps never solve the problem, but the problem isn't even a problem at all!

Could be a cool video idea to discuss actually; would have a similar vibe to this video.

[TK]

Alan (W2AEW) related video on decoupling and filtering capacitors:

[Cerebus]

THis is a timely video as I have been wondering lately about bypass caps. The usual question of why 100nF of course and where this rule of thumb originated? I've been doing a bit of reading to try to find the answer but it seems to be either never discussed or it is discussed inside very technical documents that deal with designs with far more involved multilayer PCB's.

Even Dave alluded to the fragmented ground plane on this 2 sided layout having some effect to make bypass caps unnecessary. But it was relatively ineffective at the speed of this board from the graph overlay @11:57.

I have found that the choice of cap value is also frequency dependent with both the clock signal frequency and the rise time being a factor.

With regard to 100nF is that just a common round number that is about right most of the time or would halving it to 56nF also work just as well? At under 10MHz say.

Do the lower power demand of  later generations of TTL post 7400 and 74S00 need lower value bypass caps or is it more frequency/rise time than power consumption dependent? Or does lower frequency mean larger caps?

If anyone knows of a link to a good basic discussion of this that may address some of my questions I'd certainly take a look at it.

Or failing that, this is my simple question. In a circuit similar to the Gigatron (ie not known to work without bypass caps at all) would 56nF caps have served just as well?

As part of the background to this, I don't think that it's an accident that an old ceramic through hole 100nF, or poly 100nF, neatly and snugly fits across the end of a 0.3" DIP package.

Often on things where I've had cause to actually calculate (or select on test) bypass caps, less than 100nF has often been fine but I've gone with 100nF any way as (1) It's safe, (2) It's one less value to add to the BOM - it's a lot cheaper to buy a huge number of 100nF caps relative to a few 22nF, 47nF, 56nF etc. The only time bigger bypass caps than strictly necessary will bite you in the backside is if you manage to hit an impedance sour spot (as in the opposite to a sweet spot) where your frequency of interest is at or above the cap's self resonant frequency.

[T3sl4co1l]

FYI, this is how you calculate a bypass cap:

1. Isolate the IC in question.  This avoids discussing the PDN (power distribution network) as a whole.

Isolation is provided by a relatively large value inductor, followed by a bulk cap with ESR matched to the inductor.

This gives a subnet impedance that peaks at the resonant frequency 1 / (2*pi*sqrt(L*C).  The resonant impedance is sqrt(L/C), which is also what the ESR is chosen as.  The peak Q is around 1, and so the impedance peak is close to sqrt(L/C) as well.

2. Consider the loads on the IC.

For CMOS logic, the normal DC load is minuscule.  Pullups are generally weak.  LEDs are weak to heavy (depending on value).  Transmitters driving terminated lines are heavy.  Whatever the load current is, consider the effect of all outputs switching on or off at the same time, in whatever worst-case pattern the circuit is capable of.  This is a load step transient.

3. Consider the shoot-through of the IC.

This is normally not a big deal for TTL, CD4000 or 74HC families.  The latter may be on the order of 10mA for a few ns.  Punchier families, like 74AC, LVC and so on, can draw much more, up to 100mA for a few ns (or less).

4. Consider the supply voltage ripple that is allowable.

For general purposes, 5% is probably fine.  Even 10%.  That is, 0.5Vpk out of a 5V supply.  If you need stable, low-jitter timing, you may need 1% or less ripple.  (You may also need additional isolation -- not just bypass, but a local LC filter to keep supply noise away from a critical part.)

5. Put it all together.

We can use a charge argument to find how much capacitance is necessary to deal with shoot-through.  Even for 74AC, at 5V supply, 1% ripple, the shoot-through is only 100mA * 2ns = 0.2nC.  Since Q/V = C, and delta V = 0.05V, only 4nF is required.

For load step conditions, we need to calculate the AC impedance of the supply.  How much is required?  Simple: if the worst-case step change is 20mA, and delta V = 0.05V, then we need |Z| < (50mV / 20mA) = 2.5Ω.

Notice that we cannot get to a single capacitor value from here.  We have an impedance, but no frequency.  The frequency is "all" -- we need a resistance!

We can only get a resistance to the IC, by using a regulated DC supply, an inductor with DCR < 2.5Ω, and a bulk capacitor with ESR < 2.5Ω.  The inductor value is chosen to be smaller than R^2 * C, so that ESR dominates at higher frequencies.

6. What else?

Notice this ignores stray inductance.

In a real circuit, the characteristic impedance of traces, component bodies, vias, pins, etc. is modest, in the ballpark of 100 ohms.  All transmission line structures, no matter how short, have stray inductance, proportional to the length and the characteristic impedance.

It's important to note these simple facts about transmission lines -- because this way, you can determine, for any layout, what stray inductances to expect, by using trace width formulas / calculators.  It's also important because, if you go out of your way to make a pathologically low impedance -- like a super wide trace -- that you can expect not just somewhat lower inductance from it, but proportionally lower!*

*But not actually proportional, because of end effects.  It's proportional when the length is much longer than the width.  A single via dropping into a 5cm wide trace, isn't going to spread out instantly, it's effectively got rings of wider and wider traces around it until they reach full width.

When we include these stray inductances in the circuit, we have to include their voltage drops.  For the load step condition, the rise time factors in: for a 20mA, 1ns load step, and the same 1% ripple, we need L = delta V * t_r / delta I = (50mV) * (1ns) / (20mA) = 2.5nH maximum.  That's just a few mm of trace length -- indeed, just a few mm of pin length -- it is the loop from GND, through the bypass cap, to VCC, through the chip, back to ground, that contains the relevant total inductance.  For such a demanding application, you can only solve it this way: use a 74LVC1Gxx surface mount part (or the equivalent TinyLogic), use an 0603 SMT chip cap right beside it, and flood around and beneath the components with ground plane.  This probably won't quite achieve 2.5nH total, but it will be as close as you can get.

In this way, we can immediately rule out certain possibilities, like 74AC in DIP packages -- the risetime isn't quite as sharp as 74LVC, but the gulp is huge, and you physically cannot achieve a 1% ripple factor at the device, due to packaging alone!

7. So what?

If you aren't performing this analysis -- at best, you're lazy.  At worst, you're irresponsible!

There can be no simpler rule of thumb here: any simplification must miss critical information, like stray inductance.  The result would be fragile under, not even pathological cases, simply cases where the assumptions (used to make that simplification) are broken.

For the regular case of 0.1uF (approx. 50mΩ ESR) caps, yes, they should be placed as close to the IC as possible, that's fine; but the spacing between caps matters.  If we space them such that the stray inductance is larger than, say, 50nH, we may have impedance peaks high enough to be problematic (i.e., Q ~ 15, Zpeak ~ 10Ω).  This is only a couple inches of trace length!

One final note: notice I haven't made any reference to self-resonance here.  SRF is meaningless.  The behavior of the circuit depends on the properties of all components involved.  What is meaningful, is the properties: ESR and ESL, stray inductance, all that.  We could use the SRF to solve for ESL (an 0.1uF with SRF at 10MHz has ~2nH ESL), but we can also just as well assume it by physical properties (length, namely), and get close enough for hand-waving's sake!

Tim

[EEVblog]

Very interesting video, really enjoyed it! However, I have to say that the glitches at 14:38 are being blown out of proportion a bit.
*snip*

Well yes, and that's a whole other several hour long video if you wanted to cover every such scenario.
It's likely that some of the ground stuff I was seeing was caused by the lack of bypassing, and saying "runt pulse" probably wasn't the best term to use here. It was a just a quick look to see if I could anything.

[EEVblog]

7. So what?
If you aren't performing this analysis -- at best, you're lazy.  At worst, you're irresponsible!

That's a bit of a stretch.
Come on, seriously, even you aren't going to do this for most general designs.

[EEVblog]

THis is a timely video as I have been wondering lately about bypass caps. The usual question of why 100nF of course and where this rule of thumb originated? I've been doing a bit of reading to try to find the answer but it seems to be either never discussed or it is discussed inside very technical documents that deal with designs with far more involved multilayer PCB's.

It's the same reason why 10k is the rule of thumb pull-up resistor.
a) Nice round value
b) You'll have a ton of them in the junk bin
c) High enough not to use too much power, and low enough to make it fairly "solid".

100n is the standard for similar reasons, but add in that it was one of the highest value ceramic caps back in the day and still cheap and readily available. Generally the higher value bypass cap is, the better, package and connection being equal.
So 100nF was the highest value that was cheap and available, and basically still is.
Even today you wouldn't use 1uF or 10u ceramics everywhere for bypassing because as they are more expensive, you'd save those for bulk bypassing or cases of big current gulping devices like FPGA cores.

With regard to 100nF is that just a common round number that is about right most of the time or would halving it to 56nF also work just as well? At under 10MHz say.

Yes, the value doesn't make much difference.

[SL4P]

How about the bypass caps muting the effect of near-field induced transients - not necessarily sourced from the board under test...?

[Fungus]

Dave: "Obviously can't probe everything..."

Not enough oscilloscopes? 

[T3sl4co1l]

7. So what?
If you aren't performing this analysis -- at best, you're lazy.  At worst, you're irresponsible!

That's a bit of a stretch.
Come on, seriously, even you aren't going to do this for most general designs.

It only takes a few minutes to inspect a route, towards the end of layout, and determine if more capacitors are needed (or fewer!), and what kinds.

Tim

[T3sl4co1l]

How about the bypass caps muting the effect of near-field induced transients - not necessarily sourced from the board under test...?

Or making them worse?   All about loop area between ground, trace and load.  Nice thing about ground plane is it serves as a shield, even though, geometrically speaking, it is beneath the traces.

As far as minimizing loop area, keeping the low impedance connections (i.e., bypass caps) near the load, does generally tend to have this benefit.

Tim

[SL4P]

Good points,

[bsdphk]

Is the Gigatron really built with "real" TTL, as in "7400", or is it one of the subsequent more advanced technologies like LS or ALS ?

The "one bypass per chip" rule-of-thump came to be because the original TTL chips sufferer "shoot-through" when their output stage changes state.

For a brief moment, measured in (fractions of) nanoseconds, both the top and the bottom transistor conduct at the same time, essentially shorting the +5V rail to GND.

This was a major part of both the power-consumption, speed-limit and EMI nightmare of the original TTL family chips.

Avoiding shoot-through was the major part of the "LS-revolution" which generally does fine with two layers of the PCB acting as bypass capacitor.

However, in large, dense and fast designs, bypass caps may still be required, typically near the chips which drive the largest nets/loads.

If you want to follow this video up:  Put a scope on the supply current of a 7400, 74S00, 74H00, 74(A)LS00 and 74C00 with a MHz-range signal, and watch the difference.

[tszaboo]

Is the Gigatron really built with "real" TTL, as in "7400", or is it one of the subsequent more advanced technologies like LS or ALS ?

It is using 74HCT according to their website.

[insine]

Dave, maybe you could do the same with Raspberry Pi?
Might be interesting.

[ataradov]

It was common to see Russian BK-0010 computers without any bypass capacitors, since they were cut by precious metal scrappers. And they absolutely did not work. Some would kind of boot, but will glitch in finny ways. The significant part was probably SDRAM. Those memory chips from the 80s are huge power hogs, and power line becomes just a mess without bypassing.

I've also seen modern MCUs fail without sufficient bypassing. Those things fail in a bit less obvious ways, so the method "remove until it fails" is not going to work, or investment in testing will cover any savings on capacitors. So the method "at least one capacitor per power pin" remains valid.

[MisterDiodes]

Dave,
Interesting test on the Gigatron, but you don't want to give the impression that bypass aren't needed.  They are.  Part of why you add bypass caps is to keep the local chips operating correctly, but you're also looking at noise immunity to external EMI coming INTO the board, as well as radiated EMI from the board - acorss all operating temps.  We've seen several examples where a board lockup was occurring say when the nearby soldering iron was at idle, clicking on and off...and solving the problem on the PCB in question with more robust and wideband bypassing.  Another example would be when you're at EMI testing and realize you can solve a radiated emissions problem with a few more bypass caps at a better location (basically adds no cost to the BOM) vs adding another ferrite or shield.  It happens.  Just depends on the situation.

Generally when testing a CPU system for adequate bypassiing you'd be running some sort of memory randomized stress test that includes lots of random events, memory writes, I/O access, various timing loops, exercise all current loops, etc.  And you let that run for a while - days and weeks if required.

I'm wondering of the Gigatron would still do the Mandlebrot set to completion without any bypass caps for example.  It might, since it's really not super high speed...but it might glitch too. 

Just running a simple loop on the Gigatron and declaring bypass caps aren't required is maybe not the very best example.  But thanks for the videos!

RE: Size of bypass caps:  Use what is necessary - and you'll find that out during board testing.  100nF per power pin set is common starting value, but especially around FPGA's faster CPU's etc. you see a more wide band approach where you'll need say a 10uF tant, a few 1uF, then maybe some 100nF, 10nF and maybe some 100pF etc. around the chip pad layout.  Possibly even a ferrite bead or two.  The manufacturer of the chip will usually give some guidelines or look at the reference circuit etc.

Faster ECL / I2C / SPI / LVDS / etc bus chips are typically a little more sensitive to proper power bypassing too - in addition to proper signal line termination of course.

There is nothing more annoying tracking down some sort of random, intermittent or "once a week" failure or board lockup that was due to some PCB designer trying to be cheap on the bypass caps.  Especially when you're in software development on a new device and you can't tell if that last crash glitch was software...or hardware related?    Ugggh. 

[T3sl4co1l]

I had that, back when I breadboarded a Z80:



With it running a text scrolling routine, it was fine.  Then I added a chiptune program (running from the timer and interrupt), and it might go a week before freezing.  Hmm.  Then I added a bit-bang LFSR (noise generator), and it might go hours, it might go days, of run time.

As you can(?) see, it's well bypassed: one every chip or two, plus extras between rails and along the side.  I never saw a change in stability by adding or moving caps.

The problem is not supply quality, but signal quality.  No ground plane.  Well, no good plane.  The black binding post is connected to the metal backing plate (I ground off the paint on the back side), but it has a long wire tying it in.  Probably anywhere a lot of signals (address and/or data) are changing simultaneously, a lot of displacement current is shoved into the plate (and neighboring traces), and everything hiccups.  Double-tapping a clock would be a pretty obvious problem, there may be poorly resolved timing issues as well (Z80s usually go together with classic parallel bus chips very easily, I'd have to review the thing in detail to see what the shortest critical time is).  Whatever it was, it was a CPU crash, maybe bad power, maybe invalid opcode, maybe infinite loop (I don't think there was any bus activity, but I don't think I ever scoped it).  Could even be signal bounce upsetting the CPU, because ESD diodes.  Oh, and that was an NMOS (dynamic) version CPU, so it's not happy with an out-of-whack clock.

So as you can see from this example, having a solid ground plane is a far higher priority.  I shudder to think of the olden days where TTL was routed on two-layer boards, with power buses (VCC and GND) interleaved in rows beneath the chips, and signals spanning between rows -- what an EMC nightmare!  The poor things probably required a shield (a ground plane!) just to operate, let alone meet emissions.

But don't take my word for it.  We should be so lucky as to work in a field where everything can be calculated, often with handy (and still reasonably accurate) shortcuts.  Everything can be measured, often with just a scope.  Develop the intuition for yourself, and reinforce it frequently with measurement.

Tim

[David Hess]

THis is a timely video as I have been wondering lately about bypass caps. The usual question of why 100nF of course and where this rule of thumb originated?

100nF is larger than required for any reasonably small package and still within the "cheap" part of the capacitance in a single part.

With regard to 100nF is that just a common round number that is about right most of the time or would halving it to 56nF also work just as well? At under 10MHz say.

When dealing with SSI (small scale integration), 2200pF is often plenty.  If you pessimistically figure 4 outputs driving 27pF each simultaneously, then driving 108pF total output capacitance will drop the supply voltage by 5% with a 2200pF of decoupling close to the package.

Do the lower power demand of  later generations of TTL post 7400 and 74S00 need lower value bypass caps or is it more frequency/rise time than power consumption dependent? Or does lower frequency mean larger caps?

At least with SSI and MSI, it is more about how many outputs are driving how much capacitance and what supply voltage bounce is acceptable.  Transition time also matters and this is often carefully controlled; with slow transition times like you will find with slower logic, the decoupling requirements are lower.  In my example above, I was pessimistic about transition times.

The rules are different for large ICs.

Or failing that, this is my simple question. In a circuit similar to the Gigatron (ie not known to work without bypass caps at all) would 56nF caps have served just as well?

With TTL?  Almost certainly.  I typically use 0.01uF for SSI packages but if the price difference between 0.1uF and 0.01uF is insignificant, then there may be no reason to use the smaller part.  I don't think I have ever designed in anything smaller than 0.01uF because there is no cost savings, however ...

One design I saw had odd but standard values of 5% film capacitors used for decoupling.  The idea was to use the capacitance and series inductance of the package and layout to notch out specific frequencies for improved EMI compliance.  I do not remember if that was part of the original design or changed later.

[jnissen]

Dave, I'm surprised you were looking at signals for a power integrity marker. Sure you can see some effect but why not probe the power lines as that will be the real "signal" that will be affected. I tend to use low impedance rigid coax for these measurements directly into 50 ohms at the scope. The 50 ohm load of the scope is going to seem like a rather high impedance probe compared to the supply impedance. Then you use the trigger levels to find the peak offending drop out or ground bounce. Using a high impedance probe for supply investigations can often pick up more noise due to the fact the loop area typically increases. The rigid coax also acts somewhat of a low pass filter with the 50 ohm load and input capacitance. BTW - do this only on scopes that can handle the peak to peak input voltage while in 50 ohm mode.

One other note: At 30:50 in the video you mentioned these were "real little things happening in the circuit".  I'll assume you know exactly why your getting the knee in the signal. That is the transmission line and the knee in the signal is telling you you probed closer to the source side of the transmission line as opposed to the destination. Surely you recall your t-line fundamentals from school? May be a good video discussion to go over as seeing signal integrity in the real world often drives home the theoretical learning of signal propagation fundamentals. 

[KE5FX]

Dave, I'm surprised you were looking at signals for a power integrity marker. Sure you can see some effect but why not probe the power lines as that will be the real "signal" that will be affected.

Absolutely.  Vdd is a signal.

I ran a few experiments the other day with a slightly more modern CMOS part:



Yes, you can get away with less bypassing than the manufacturer recommends.  Usually a helluva lot less.   But: (1) 'Mad Man' Muntz didn't need to explain himself to the FCC; and (2) do you feel lucky, punk?

[David Hess]

I tend to use low impedance rigid coax for these measurements directly into 50 ohms at the scope. The 50 ohm load of the scope is going to seem like a rather high impedance probe compared to the supply impedance. Then you use the trigger levels to find the peak offending drop out or ground bounce. Using a high impedance probe for supply investigations can often pick up more noise due to the fact the loop area typically increases.

There is nothing to prevent using a high impedance probe with a coaxial connection and when done properly, they will return results similar to a low-z probe when making this measurement.  This is one of the rare cases where the larger capacitive load of a passive probe does not matter.

A larger problem is relying on any ground with a single ended probe because ground bounce is a real problem.  Low voltage differential probes are ideal for this application.

If you do use a single ended probe of any kind, do an additional measurement with the probe tip and ground connected at the ground point you have selected.  The ground bounce and common mode noise may be so great that further measurements without a better probing technique are useless.

[ignator]

My experience with decoupling capacitors was for compliance to radiated emissions in avionic products. Sitting in a screen room, I always found the need of more capacitors. And it's the wrong place to be adding them in. It was always difficult to get engineers to place them correctly in the layout so that the IC was drawing charge from the bypass capacitor, and not the connected power and ground plane. PCB designers would just scatter them around with no special routing technique (although I've seen schematics where the capacitors are all shown in a array block on a page, and the designer placed them that way on the board).
As clock speeds morphed from 6Mhz (start of my career) to 100Mhz (retirement) and beyond, multiple capacitors were needed. A large one for the major charge source, and smaller ones for the high frequency charge movement. If you look at the problem as charge transfer, every time an output driver toggles, and this driver has to charge the board capacitance to the connected gates, and these gates all have input capacitance, and the IC is maybe an octal part, my game plan was to calculate the total load capacitance, and design in a decoupling capacitor of 5-10x that load capacitance. To properly connect the part, the power had to be routed to the decoupling capacitors first, then large low inductance traces to the power pins of the IC. The idea was to make the decoupling capacitor the source for the charge, and not the power planes. And that was always hard to get the PCB designer to do, as they liked to turn on autoroute. If you could effectively keep the RF charge noise from making it to the power supply, compliance to radiated emission limit line could occur.

[T3sl4co1l]

(although I've seen schematics where the capacitors are all shown in a array block on a page, and the designer placed them that way on the board).

Better to laugh than to cry at such things...

The idea was to make the decoupling capacitor the source for the charge, and not the power planes. And that was always hard to get the PCB designer to do, as they liked to turn on autoroute. If you could effectively keep the RF charge noise from making it to the power supply, compliance to radiated emission limit line could occur.

FWIW, not the best plan: power planes are better capacitors than the components are!

Indeed, bypassing planes, one needs to be careful that the bypasses themselves don't make things worse.  A plane is typically a few nF (obviously, depends on size and thickness) of nearly-ideal capacitance, with a modest Q at most frequencies (>20?), and every connection to it incurs at least a few nH because of via and body length.  So, of course -- use the same analysis as ever: check R, L and C and make sure it's dampened!

Incidentally, PCB-level bypass becomes impossible above maybe 100MHz, so you shouldn't get overly worried about supply impedance up there.  Anything that needs that kind of power bandwidth, must have onboard bypasses.  FPGAs and CPUs typically have wide-format SMT chips, or LGAs even (checkerboard pattern connections on the caps -- lots of interdigitation!), built into their packages.  The interposer, whether made of fiberglass or ceramic, is much finer pitch than anything we would pay for on the size of a PCB, so can deal with much higher frequencies.  This continues onto the chip itself, where the top two metal layers (say) might be a checkerboard pattern, giving maybe a whole nF or more of local bypass.

On that note, you can assume such a load has some ESL (pins and routing), then R || C.  The R is more or less the DC load resistance (logic gates have a resistive characteristic), and the C is whatever all the junctions and bypasses total (so, it could be many nF, even some uF for VCORE on big CPUs).  Don't forget to consider this in your analysis!

Tim