What tggzzz said; but note those 1k resistors will limit the rise/fall times so slow that you can't achieve the communication at 50Mbps because the signal settles slower than the time required to transmit one bit. (I'm confident enough to guesstimate this. Say, assuming even just 20pF trace & pin capacitance, R*C = 1000 ohm * 20 pF = 20ns, actually equal to your period at 50MHz, so wasting the complete period just to settle to 63% of the target voltage!)
OTOH, wasting some 5-10% of the period available for smoother transitions does help with EMI, so having some resistance is desirable.
I would do a very roughly impedance controlled line, i.e., use a 4-layer (or more) design because you likely have it already (or greatly benefit from it in such FPGA project), look at the stackup your board vendor uses, then use some sort of trace width calculator so I end up at some known impedance such as 50 ohms or 70 ohms, roughly.
Then, use series termination (resistor in series with the driving pin) approximately the trace impedance minus the output impedance of the CMOS output driver. The latter is actually a range depending on unit variation, temperature, etc., and not properly specified, if at all; assume the lowest possible here so that we rather oversize the resistor than undersize it, to prevent ringing. For example, assuming Zout = 10 ohms, Ztrace = 60 ohms, use a 50 ohm series termination resistor.
The larger it is, the slower the transitions, the smaller the current spikes to drive the line, the less ringing you see. I would use some 47R to 68R.
But at 50Mbps transfer rate, you don't have a huge margin to slow down the edges, so 1k will definitely fail.
Your 1k together with parasitic capacitances and junction diodes provide indeed better ESD protection than adding just some 50R. But seeing this is on-board communication, just internal signals, such protection isn't usually used because it would be quite hard to zap those internal signals (normal board handling precautions apply!) If you went that way, you would want to consistently protect every signal and that would make everything impossible. (IC manufacturers add enough protection into their ICs so they handle "typical" board handling conditions.)