USB power filter inrush current problem

[tapirath]

Hi,

I'm trying to implement a filter on my power line (coming from a 5V@3A USB wall adaptor).
The idea is to filter the power against high frequency noise (>100Khz) and fed it to 2 separate 3.3V LDOs (250 mA each) and to a Raspberry Pi (up to 2A) thus I'm needing a big bulk capacitance on one end of my filter as shown in the schematic:


The problem with it is that I get huge inrush currents on my damping resistor and possibly on my LDOs too (assuming RPi already has a mechanism to overcome it) as shown below.


What can I do to protect my components against this?

PS: I deliberately didn't use an electrolytic cap as I can't seem to find reliable data on their ESR values and no SPICE models to test. So I thought it's better to implement my own damping resistor with the biggest MLCC I can find.

[tapirath]

I didn't have a series resistance setup. I'm using piecewise linear voltage source so I can acutally precisely setup rise time. At the moment I have it set up at 5V in 1us (it rises linearly). What would be a realistic rise?

[thm_w]

How much greater than 100kHz? Might be better off with an inductor over a ferrite bead.

Normally with USB device you'd want to limit to 10uF. But considering you're powering off a USB supply, should be OK with a few hundred uF of electrolytic capacitors. One on the input and one on the output (CLC).

[T3sl4co1l]

More to the point, a ferrite bead won't do anything at 3A, due to saturation.  You need a special model to see that; almost all FB models are AC only, and often poorly fitted at that (like, single RLC).  (At least, not *any* plain text models that I've seen; I've had to build them myself!)

Not sure what the ramp rate is modeling; a hot-plug event is much faster (mechanical connections close in sub-ns, at least to some degree of "close") but also requires modeling cable inductance (figure ~0.5uH/m of length), and probably source capacitance too.  Ramp rate of the supply itself (startup) is likely to be some ms, negligible for dynamics here.

Chargers are often a bulk cap directly off a flyback converter, so the output ripple (DM) can be pretty mediocre, but also most loads won't much care (e.g. more regulators).  So first of all, you should have that justification in place: how much ripple do you really need, and at what frequencies?  Otherwise the filter can be the trivial case -- an utter passthrough -- and I mean that as engineering best practice, because, without a need, there's nothing to engineer, good job, next!

As for CM (common mode), this filter does absolutely nothing -- and CM is often the worse thing at higher frequencies (MHz+) and for signal purposes (where high frequencies get rectified into low-frequency noise or DC offset).  That can be trickier to deal with, because chargers often skimp quite severely on filtering in the first place, and also tend to use a relatively large Y-cap meaning there's significant AC mains leakage (fractional mA) -- the latter is what causes the tactile vibrating / rubbery feeling you may get when handling a cellphone on the charger.

Tim

[tapirath]

More to the point, a ferrite bead won't do anything at 3A, due to saturation.

Is it still the case if I'm using the FB in picture which is rated up to 12A@85C?

Not sure what the ramp rate is modeling...Ramp rate of the supply itself (startup) is likely to be some ms, negligible for dynamics here.

The ramp rate model is just something I got from reddit which in hindsight maybe wasn't the best source of information. However looking at the capacitor current formula I see that the rise time is part of it:

Code: [Select]

I = C × dV/dtAnd indeed if I increase the 1us rise time to 1ms in the above simulation the current level drops to mA level at the damping resistor. Or am I completely off base?

Thanks for the explanations! Was your answer cut short somehow?

[tapirath]

How much greater than 100kHz? Might be better off with an inductor over a ferrite bead.

Admittedly I don't know. My LDOs which supply analog part of the circuit have good PSRR so I'm not worried about that part but my readings led me to believe that I also need to have some attenuation on MHz range even up to GHz range for my high-speed digital circuit (RPi in this case)
 

[T3sl4co1l]

More to the point, a ferrite bead won't do anything at 3A, due to saturation.

Is it still the case if I'm using the FB in picture which is rated up to 12A@85C?

That's strictly the thermal rating, for whatever (usually 40C) temp rise -- it has no bearing on saturation current.

Murata does not provide bias data for this part (or most any of them, sadly; at least not in an accessible format, maybe their "bias tee" tool contains such data but good luck with that.

The nearest Laird equivalent is probably HI1206T500R-10, although rated only 6A.  It shows about, hm not 50, closer to 45 ohms at 100MHz, but whatever; that's at zero bias.  At 1A, it's down to about 32 ohms, so, nearly -30% impedance -- a typical threshold to consider "saturated".

Lower impedance beads do tend to retain impedance better, and it's noteworthy that impedance is still droppping over the 3, 4, 5A range; it doesn't saturate suddenly, but is roughly inverse proportional to bias.  (Which makes sense, as the construction is probably a single wire link through the middle of a ferrite block: the inner radius closest to the wire saturates first, and more further out as bias goes up.)  But two things remain true:
1. you don't get the same attenuation under load as at no-load, it's inconsistent so you must design around both worst-case extremes;
2. if you aren't aware of this effect, you're probably not getting the value you were expecting!

Both circumstances can lead to frequency responses wildly different than expected.  I'm a big fan of avoiding surprises, and this effect is poorly documented, so I repeat it at every opportunity.

The ramp rate model is just something I got from reddit which in hindsight maybe wasn't the best source of information. However looking at the capacitor current formula I see that the rise time is part of it: \$I = C\frac{dV}{dt}\$
And indeed if I increase the 1us rise time to 1ms in the above simulation the current level drops to mA level at the damping resistor. Or am I completely off base?

Indeed.  However, you can try it for a say 10ns rise into a 0.6uH inductor and the rest of the circuit, modeling the hot-plugging of [an inductive] cable 1m long.

Even more interesting is when the filter capacitors are high-K ceramic, which similarly saturate (C decreased) under V bias.  The resulting peak overshoot can be several times the supply!

Tim

[tapirath]

That's strictly the thermal rating, for whatever (usually 40C) temp rise -- it has no bearing on saturation current.

Murata does not provide bias data for this part (or most any of them, sadly; at least not in an accessible format, maybe their "bias tee" tool contains such data but good luck with that.

The nearest Laird equivalent is probably HI1206T500R-10, although rated only 6A.  It shows about, hm not 50, closer to 45 ohms at 100MHz, but whatever; that's at zero bias.  At 1A, it's down to about 32 ohms, so, nearly -30% impedance -- a typical threshold to consider "saturated".

Lower impedance beads do tend to retain impedance better, and it's noteworthy that impedance is still droppping over the 3, 4, 5A range; it doesn't saturate suddenly, but is roughly inverse proportional to bias.  (Which makes sense, as the construction is probably a single wire link through the middle of a ferrite block: the inner radius closest to the wire saturates first, and more further out as bias goes up.)  But two things remain true:
1. you don't get the same attenuation under load as at no-load, it's inconsistent so you must design around both worst-case extremes;
2. if you aren't aware of this effect, you're probably not getting the value you were expecting!

Both circumstances can lead to frequency responses wildly different than expected.  I'm a big fan of avoiding surprises, and this effect is poorly documented, so I repeat it at every opportunity.

That's a really good explanation! I think I'm going to experiment with inductors instead. I see they also have a saturation current but the curve looks much more stable on the range I'm interested in (1-3A)

Indeed.  However, you can try it for a say 10ns rise into a 0.6uH inductor and the rest of the circuit, modeling the hot-plugging of [an inductive] cable 1m long.

Even more interesting is when the filter capacitors are high-K ceramic, which similarly saturate (C decreased) under V bias.  The resulting peak overshoot can be several times the supply!

Tim

So according to Murata a X7R 22u cap will have around 20% capacitance drop at 5VDC. I think I can design around that.

Overall do you think I'm overthinking it just to power a Raspberry Pi (assuming LDOs will already take care of the 3.3V supply)? Or am I on the right track?

[Georgy.Moshkin]

https://www.murata.com/en-us/products/productdetail?partno=BNX016-01

I found schematic of this emi filter intetesting. I think that capacitor they are using is less than 47uF, and attention above 100 kHz is good.

[T3sl4co1l]

Huh, I wonder if that's common mode at the input (the test diagram seems to suggest as much, driving pins 1/3 with a balun), i.e. the pins are choked together, not just individually.

Those filter assemblies have the same drawback, attenuation varies with bias -- in this case both voltage and amperage.  The reduction with the smaller "dogbone" style passthrus can be quite surprising (if one isn't aware of saturation).

Overall do you think I'm overthinking it just to power a Raspberry Pi (assuming LDOs will already take care of the 3.3V supply)? Or am I on the right track?

If it works with the charger as-is, and you aren't seeing excess noise on like audio in/out, I doubt it matters.  And if it doesn't work with the charger, it's unlikely that noise filtering will solve it.

I'm not intimately familiar with every rPi in existence, but I have heard they are finicky about voltage, mainly in the downward direction, i.e. too-long and too-cheap cables drop below 5V at max load current, and it's set to turn off / reset pretty nearby (4.5, 4.75V, something like that??).

Tim

[tapirath]

For what it's worth, I've changed to a 4.7uH inductor with 2 big 47u caps and a soft start via a PMOS. I already had a PD sink controller in my plan (CH224K) which turned out to have an open drain output when the power negotiation is done so I've used that to trigger the PMOS. I'm happy with the tremendous attenuation I get and looks like there are plenty 4.7uH inductors with relatively stable curves on 3A current.

[tapirath]

So the PMOS (DMP2008UFG) I use has the below gate threshold voltage

and indeed as seen in the simulation it starts turning on once the gate-source voltage is above -0.7V (I guess the model I use just averaged min-max)

[T3sl4co1l]

More to the point, K2 is probably off in .AC.

Tim

[tapirath]

Right, but threshold voltage is just the start of turn-on; S-D resistance is still pretty high. You have to drive it significantly past Vth for full conductance.

True. removed R5 and increased R7 to 470k

[tapirath]

More to the point, K2 is probably off in .AC.

Tim

Indeed, I still have a lot to learn about spice simulation. For freq analysis I removed the switch and the curve looks more reasonable.