Understanding an inductor turn-off transient

[shapirus]

I am experimenting with a simple fixture for oscilloscope made for measuring inductor saturation current. The principle is using a scope to observe how current passing through an inductor changes over time. The point where the rate of change increases (usually quite prominently) is I_sat. Helper components here are a current sense (shunt) resistor, a MOSFET used as a switch, a gate driver circuit and a source of short pulses to turn the switch on and off.

Here's the schematic:




I built it on a solderless breadboard first, then made a proper PCB to verify that general behavior does not change and it wasn't caused exclusively by the breadboard's parasitics.

The effects that I am curious about and some of which I do not understand are not visible in SPICE (ngspice) simulation, so they must be coming from something unaccounted for.

Here's what I see on the scope. Control pulse is a 0..5V signal coming from a signal generator. The inductor is a drum-type (no idea what core material) 47 uH.


First, control pulse (channel 1, green) and VSENS (channel 2).




...and, respectively, SW_GATE and VSENS:





Everything before the turn-off edge is expected, and then we see a huge reverse current spike. Let's have a closer look.

1) Ch1: control pulse, ch2: VSENS




2) Ch1: SW_GATE, ch2: VSENS



(note that the vertical scale of ch2 is different between the two.)




Part 1: the big negative spike.

Part of what I'm seeing here can probably be explained by the return current of the discharging gate-source capacitance of the switch transistor (2.2nF). However, the charge it stores is very far from being able to produce such a big spike. I tried to connect a 15nF capacitor between gate and source: it made this spike higher, but narrower. This makes me think that this effect is a combination of multiple factors, one if which, but not the major one, is the gate capacitance.

So, what is responsible for the majority of this energy flowing in the reverse direction? Inductance of the sense resistor itself? I doubt it, it should be very small. It's coil-like, yes, but it's only 10 turns of wire without any core (I don't have other suitable shunts at hand to confirm this).

...another question is how to suppress it, but the answer to this should come with the understanding of what causes it.

Part 2: things that happen before going below zero.

There's that drop at VSENS which aligns with the falling edge of the control pulse. Why does it happen exactly then, instead of when the switch transistor's gate voltage drops below ~Vth? Instead, it first drops to zero, following the control pulse, then bounces back (why?) to where it was, and then, following the gate voltage fall (and that's when I would expect it to), finally falls to zero, which is followed by the negative spike.
Why does this happen? I have verified that it's not some kind of scope inter-channel interference by disabling channel 1 and detaching the probe.


Two more screenshots:

1) Control pulse + MOSFET drain:




2) MOSFET gate + MOSFET drain:

[jwet]

These traces would make more sense if your channel 2 scale was off by 10x- are you sure of these values.  The tell tale hint is that the sense resistor is .1 ohm and the Ron is .02, 5 times lower.  I would expect drain voltages (ref to source) to be 5x lower than V sense.  Are your drain voltages measured relative to ground or source?

I think once you get the scales correct, you'll find that this negative spike is current from discharging the gate as you suspect.

[shapirus]

These traces would make more sense if your channel 2 scale was off by 10x- are you sure of these values.

Yes, quite certainly. I double checked everything. The 2nd channel trace is at 12 volts all right when I probe the positive supply rail.
Additionally, the positive side of the sense resistor trace matches the spice simulation very well (I would even say surprisingly well) as far as the pre-saturation rate of change of the current flowing through the sense resistor:



R2 here represents DC resistance of the inductor -- I hope that's the right way of representing it. R3 is for the mosfet's drain-source resistance. Too bad this inductor model doesn't support simulation of core saturation, so we can't see it there

The tell tale hint is that the sense resistor is .1 ohm and the Ron is .02, 5 times lower.  I would expect drain voltages (ref to source) to be 5x lower than V sense.  Are your drain voltages measured relative to ground or source?

All voltages were measured relative to ground. Now that's an interesting thought. I'll capture a trace of voltage between source and drain as well to see what happens on the transistor alone. Too bad my scope has only two channels, so I can't capture the control pulse on ch1 and then use ch2 and ch3 to do the subtraction between source and drain to see both the falling edge of the pulse and the signal of interest on the same screen, so it'll have to be a single trace.

I think once you get the scales correct, you'll find that this negative spike is current from discharging the gate as you suspect.

Nope, there is definitely something else in it. It may still be some capacitance, but definitely not the Cgs alone.

Let's make a rough estimation via comparing the charge amounts.

Gate charge is 2.2e-9F * 5V = 1.1e-8C. The area under the I(t) graph... Let's say, roughly, that it's on average 20A (2V drop on the 0.1R shunt = 20A) during 600ns, so 20A * 600e-9s = 1.2e-5C. The difference is three orders of magnitude. Too much. It means that it would have to be a stray capacitance on the order of microfarads to release this amount of charge.

Hope I didn't mess up the calculations too badly.

[T3sl4co1l]

You're making an inductor divider. There is stray inductance / ESL of the shunt resistor and MOSFET.  Especially a, hand-made wirewound shunt resistor like that, is that what you've done?  Note this introduces a proportional error in your measurement: instead of V=I*R you have V = I*R + Ls*dI/dt, and dI/dt depends on total loop inductance, so as test inductance changes, so too the measured voltage changes.

If you don't care about the MOSFET switching speed (as you normally would, but, for a tester like this, who cares), the reading can be compensated by filtering the reading with an R+C lowpass, where R*C = Ls/Rs.

Tim

[Benta]

Too bad you don't show your PCB. That might bring more info.

[shapirus]

You're making an inductor divider. There is stray inductance / ESL of the shunt resistor and MOSFET.

There is, yes, but are these two high enough to cause this effect? For the mosfet, a quick search did not give me an answer about typical values, but some articles suggest that they're on the order of tens of nanohenries. If so, the effect should be negligible compared to the inductor being tested (starting at few uH).

The shunt may be a different story.

Especially a, hand-made wirewound shunt resistor like that, is that what you've done?

I used one of these: https://www.aliexpress.com/item/1005003663493453.html.

Note this introduces a proportional error in your measurement: instead of V=I*R you have V = I*R + Ls*dI/dt, and dI/dt depends on total loop inductance, so as test inductance changes, so too the measured voltage changes.

This is a good point. If the shunt's inductance is not insignificant compared to the inductor being tested, then of course its effect can't be ignored.
The question is what is its inductance. A coil inductance calculator gives results from 260 to 460 nH, depending on the total length: I'm not sure how to treat the case when the coils are spaced apart from each other. That's not insignificant, but is it enough to give the effect I'm observing? But wait a second, let me simulate it.

Here you go.




We see some violent oscillation that isn't observed in a real circuit (at least at 7.5MHz that the simulation shows, or anywhere up to ~70 MHz after which my scope is next to useless), probably because it's quickly dampened by parasitic resistances (?), however, we can notice that there is something going on at the falling edge. Let us take a closer look...



Bingo?
"Never underestimate the effects of parasitics", it seems. I just blindly assumed that the shunt's inductance was going to be negligible.

I don't have a proper LCR meter to measure it, but I have a signal generator that can output up to 60MHz and a scope that at least shows a sine wave at this frequency, and ~300 nH at this frequency is going to have an impedance of ~100 Ohm, so... maybe :)

If you don't care about the MOSFET switching speed (as you normally would, but, for a tester like this, who cares), the reading can be compensated by filtering the reading with an R+C lowpass, where R*C = Ls/Rs.

Yeah the switching speed is not important here, as long as it doesn't prevent measuring the voltage on the scope trace at the point where dI/dt rises.

This small tester is more like a proof of concept. I have an idea of creating a self-contained device that will perform measurements and output I_sat on a display. That poses its own challenges of course, but it's quite interesting. For one thing, it will require to make a fast differentiator to detect the point where the second derivative of VSENS produces a positive pulse. Sampling and holding the value is another challenge.
Simulation shows that it should be feasible, but some quite fast (hundreds of V/usec output slew rate) op amp is required.
Might even calculate the pre- and post-saturation effective inductance values based on the measured dI/dt and voltage across the inductor? Perhaps, but that almost sounds like it's too much.

Either way, even if I don't care about the negative spike (which is currently the case -- of course except for finding out what the heck is going on here), the non-insignificant inductance of this shunt will severely affect the measurements of low-microhenries inductors. It seems that a plain metal or carbon film resistor will do much better, especially considering that this gadget will never operate outside of room temperature and isn't intended as a precision tool anyway. A manganese or constantan (or even nichrome?) straight wire might do too, but I need its resistance to be high enough (0.1 Ohm is both high enough and convenient for measurements), to allow taking useful readings without (pre)amplification, and that means larger size, or extra thin wire, which means inductance again, however the latter requires calculation to see if it's going to be noticeable.

[shapirus]

I don't have any 0.1R resistors, but I do have some generic 1R 1206 SMD ones. Tomorrow I'll (try to) replace the wire shunt with 10x of these in parallel and post a report here :). Well, maybe even 1x. It will get rid of the 10x scale factor, and should work just as well for the purpose of researching the problem at hand. Hope the pulsed current of several amps during the ~15 usec pulses won't blow it up. Average power will be well within its capabilities.

[T3sl4co1l]

If exactly as pictured, it's probably close to 100nH.  This is the best calculator out there: https://hamwaves.com/inductance/en/index.html#input it doesn't have constantan as an available material, but just to get a rough figure, the difference due to skin effect and frequency (pick a roughly similar point like 1MHz) won't be a problem.

By the same token, simpler formulas (usually due to Wheeler; the linked one is such an example) won't be inaccurate enough to care.  Note that diameter and length are center-to-center dimensions, so be careful how you measure it.

The simulation has an ideal voltage source on the gate terminal, so L2 resonates with C_iss, decaying slowly due to internal gate resistance or R1.  In the real circuit, the 50 ohm source (or whatever you're using) will dampen this quickly.

The flyback voltage, essentially gives a measurement of Vgs(on) -- the source pin is pulled below GND, during the pulse, by whatever amount is required to maintain forward bias at, whatever the current was before turn-off; 2 or 3V is pretty typical.  In fact, this determines turn-off dI/dt -- the transistor can't turn off any faster than L2 allows, no matter how powerful and sharp the gate drive waveform is.  (Which is pretty damn good in the simulation: 10ns rise/fall, and, I'm assuming zero ohms as no resistor has been indicated, but I don't know if that source hides an internal stray value that doesn't show on the schematic.  A typical power transistor might have 2nF capacitance here, and a reasonably strong driver of say 5 ohms would give a rise/fall time of 20ns.)

Indeed we can use the waveform to measure the inductance a different way.  The flyback pulse is about phi = 1.8V x 490ns = 0.87 uWb, and if Ipk was 5 to 10A, we have L = phi/I = 180 to 90nH.  It's hard to say exactly what Ipk was, of course, but this at least gives support that we're in the right ball park.

A 1206 would probably handle this fine, single pulse, low duty cycle (<0.1%?); ten in parallel will do nicely, and also the wide connection thus formed will have very low stray inductance.  Bonus points for doing it on ground plane (e.g. cut a groove on the top side of a two-sided copper-clad PCB, and solder the resistors across the groove), where the stray inductance can be mere ~nH, the transistor will dominate.  (You could in turn use D(2)PAK or even PDO-8 (5x6mm) SMT packages for even lower loop inductance; the power dissipation will be less, but again, low duty cycle, who cares eh?)

Tim

[shapirus]

If exactly as pictured, it's probably close to 100nH.  This is the best calculator out there: https://hamwaves.com/inductance/en/index.html#input it doesn't have constantan as an available material, but just to get a rough figure, the difference due to skin effect and frequency (pick a roughly similar point like 1MHz) won't be a problem.

This one gives ~200 nH:


  Effective equivalent circuit
    effective series inductance @ design frequency          L_eff_s = 0.207 uH
  Lumped circuit equivalent
    f-independent series inductance; geometrical formula    L_s = 0.178 uH


This result does not depend on the material of the conductor btw. It only affects the ESR calculation. That's actually expected, I guess.

The simulation has an ideal voltage source on the gate terminal, so L2 resonates with C_iss, decaying slowly due to internal gate resistance or R1.  In the real circuit, the 50 ohm source (or whatever you're using) will dampen this quickly.

The flyback voltage, essentially gives a measurement of Vgs(on) -- the source pin is pulled below GND, during the pulse, by whatever amount is required to maintain forward bias at, whatever the current was before turn-off; 2 or 3V is pretty typical.  In fact, this determines turn-off dI/dt -- the transistor can't turn off any faster than L2 allows, no matter how powerful and sharp the gate drive waveform is.  (Which is pretty damn good in the simulation: 10ns rise/fall, and, I'm assuming zero ohms as no resistor has been indicated, but I don't know if that source hides an internal stray value that doesn't show on the schematic.  A typical power transistor might have 2nF capacitance here, and a reasonably strong driver of say 5 ohms would give a rise/fall time of 20ns.)

That's interesting. I want to retry this simulation with some reasonable parasitics added, and whatever parameters I can understand (such as capacitances) set for the transistor model, but that's for tomorrow, or whenever I have time. I believe that it should get very close to what I observe on the scope screen once all the important variables are set. Will try to adjust the pulse rise/fall time to match my signal generator, as long as they aren't sharper than my scope can detect, which, as far as I remember, is about ~16 ns, which agrees with its bandwidth limit (as far as the ability to show a sine wave goes -- not talking about measured levels here) of ~60 MHz.

Indeed we can use the waveform to measure the inductance a different way.  The flyback pulse is about phi = 1.8V x 490ns = 0.87 uWb, and if Ipk was 5 to 10A, we have L = phi/I = 180 to 90nH.  It's hard to say exactly what Ipk was, of course, but this at least gives support that we're in the right ball park.

The waveform traces for a given inductor are very repeatable, so we can get the values from different screenshots I posted: no other variables changed.
Peak current, just before the gate was pulled down, was somewhere around 9-10A.
Then, the negative peak was -31A, or -3.1V across the shunt. Within ~125ns it fell to about -1.9V, then it took ~300ns to fall to -1.6V, after which it relatively quickly died off to zero.

A 1206 would probably handle this fine, single pulse, low duty cycle (<0.1%?); ten in parallel will do nicely, and also the wide connection thus formed will have very low stray inductance.

At some point stray capacitance will need to be considered, though . The values for 1206, though, are sub-picofarad, I believe, so it may still be fine.
Regarding the duty cycle, yes, very low. Frequency can be as low as necessary for the scope to be able to trigger (ultimately a single pulse for single shot mode, or tens of Hz, below which my scope begins to fail to trigger). Pulses will be tens of microseconds, typically, save for large inductances, but those will have respectively lower currents at the point of saturation (unless I want to test some big ass power inductors, which is actually not very unlikely, but I don't have any of those yet), thus the integral value of energy dissipated will remain low.
The mosfet may be a different story. I have no idea how much current in 10us pulses it can handle. There is no datasheet, it's some fake from aliexpress, which, however, has its use. I don't care if it dies. In fact I'll be happy to find its limits.

Bonus points for doing it on ground plane (e.g. cut a groove on the top side of a two-sided copper-clad PCB, and solder the resistors across the groove), where the stray inductance can be mere ~nH, the transistor will dominate.

That's what I'm going to do. It's currently made on a single-sided board with all the traces on the botom side where all the unused area is copper-filled and connected to GND. There's already a 20 mil gap between ground and, placed next to it, the trace going from the mosfet's source to the shunt, which is perfect for 1206, and there's plenty of space to fit 10 resistors if I want to.

The only downside to using multiple resistors is that the sense terminal is located at the far end of the trace (right next to the upper pin of the shunt; the other end being the mosfet's source pin), and there's going to be a certain voltage drop gradient across the resistors, which may require adding extra solder to the trace to make its own resistance insignificant. I'm actually not sure how this gradient is going to affect the reading, and where the voltage drop signal should be taken from: intuitively I think that the contact point should be right in the middle of the row of resistors.

(You could in turn use D(2)PAK or even PDO-8 (5x6mm) SMT packages for even lower loop inductance; the power dissipation will be less, but again, low duty cycle, who cares eh?)

Yeah I might want to do this for the more complicated device, which will likely be full-SMT, except for the input cap and terminals etc., but on the other hand I already have quite a few chinese mosfets in TO-220 begging to be used, so there's no point in buying new ones specifically for this.

[Jwillis]

You must consider the gate of the MOSFET as well . At high frequencies without adequate dampening at the gate, they can ring like wildly. A gate resistor will dampen it. Higher switching frequencies at the gate may require as much as 100 ohms or more depending on the MOSFET. 

[shapirus]

I have realized that using a single 1 Ohm sense resistor will not work: at currents above 1.5-2A its voltage drop will be respectively 1.5-2V. Since the gate control voltage (about 5V effectively) is referenced to ground, it will be 5V minus the current sense drop, making the gate-source potential too low to turn the mosfet on. Too bad mosfets don't care about GND, they only "see" their source pin . The same will happen even with 0.1 Ohm resistor at high enough currents. Meh. I really wanted to use a 5 volt controlling signal and avoid using level conversion.
I'll have to rethink the design. Still, this doesn't prevent me from testing what will happen with an SMD resistor used instead of the wire shunt.

[Marco]

Just use a PMOS with a pull up resistor on the gate and NPN to pull current through the gate resistor, also gets rid of some disruption through the MOSFET capacitances to the shunt. The NMOS in the middle is ugly.

[shapirus]

Just use a PMOS with a pull up resistor on the gate and NPN to pull current through the gate resistor, also gets rid of some disruption through the MOSFET capacitances to the shunt. The NMOS in the middle is ugly.

That'll essentially be a level converter too. But yes, I am considering this option too. Only I don't have any disposable PMOS at hand, which is not a critical problem though .
An advantage of this one will be that it will need just one NPN or NMOS for the output stage instead of the complementary pair that I'm using now. The pull up resistor can be a pretty low value, considering the width of the pulses, allowing for a fast turn-off time of the PMOS. That's a bit of a downside with this approach: I want fast turn-off, but slow turn-on is fine, whereas the PMOS way you described is best suited for the opposite. A 100 Ohm resistor (already meaning 120 mA current consumed by the NPN) will mean turn-off time of the PMOS on the order of hundreds of nanoseconds, which isn't exceptionally fast.
Yes I know I can use a dedicated mosfet driver IC (and there are ones that can have 12V VDD and output, and accept 5V input) -- that will make sense in a more complicated device, but for now I'm sticking with discrete parts to learn how stuff works.

[Marco]

If you have/make an inverse of the drive signal, you can capacitively couple that to the PMOS gate to speed it up.

Or if turn on is short enough just do everything capacitively (also add a diode in parallel with the pull up resistor).

[shapirus]

If you have/make an inverse of the drive signal, you can capacitively couple that to the PMOS gate to speed it up.

This is an interesting trick, I didn't think of it. Yes, I will have the controlling logic IC outputting both the inverted and non-inverted signal. The capacitively coupled one will need to have a diode in series, though, as the controlling signal will be 5V, which is below the 12V rail (to which the gate will have to be charged).

...now that I think of it, I may not actually need the 12V rail at all. Using 5V to drive the inductor may work just as well, as long as I'm ok with the max current that it will be able to create. This will simplify things.

Or if turn on is short enough just do everything capacitively (also add a diode in parallel with the pull up resistor).

This may turn out to be too tricky to do properly, all things considered, especially that the length of the pulse will depend on how long it'll take for the inductor's core to become saturated, which in turn depends on the specific inductor being tested. I like the hint though.

[shapirus]

3D SMT, anyone?



that's ten 1206 resistors!

Curiously enough, these cheap chinese resistors, which are sold in the book-style "X values * Y pcs each" kits, are surprisingly well matched. These ten resistors, for instance, all measured within 1.000 +- 0.002 Ohm using TR-1035, end result being 0.101 Ohm between the GND and VSENS terminals.

I'll check it with the scope later today.

[shapirus]

All right, here's what we have now.

Overall view & close-up (note the zoomed in time base -- it's pretty much the practical limit of my scope).






Lesson learned: never assume that something is going to be negligible before actually verifying it. I thought that "its inductance cannot be significant" about that wire wound shunt, and didn't even think of considering that it could be the source of the problem, but we can see very well that it was a very wrong assumption.

...another lesson is that I need a better scope: I'm sure this one is hiding a lot from me, not to mention the crazy jittering at sub-100ns time resolution.

[MarkT]

You appear to be switching with 5V through emitter followers, so the actual gate voltages you'll see are about 1V for off and 4V for on.

The MOSFET appears to have a threshold voltage of 4V (or <4V?).  This could mean its almost fully _off_ at Vgs=4V.  Threshold is _not_ the on voltage, its the almost-off voltage - this is a common trap for beginners.

You need to use the full 12V supply to switch a MOSFET with a threshold of 4V.

If the MOSFET's threshold voltage was about 1 to 1.5V then 5V would be able to switch it properly.  And you'd have to use a proper MOSFET driver than pulls the gate to 0.0V for off too...

[shapirus]

You appear to be switching with 5V through emitter followers, so the actual gate voltages you'll see are about 1V for off and 4V for on.

In fact, it's a bit different. Off-state gate voltage is about 600 mV, which agrees with the p-n (E-B) junction potential barrier of the PNP transistor, and on-state at 12V supply voltage is about 5.5 V, for which I lack immediate understanding (I will need to figure this one out). With 5V supply voltage, it goes ~500 mV below 5V.

Here's what the scope is showing. All ground-referenced. Control pulse is 5V, shown at channel 1. Don't trust the voltage readings too much, it's not too precise (but still fine for estimation).

1. 12V supply: gate voltage




2. 12V supply: VSENS




3. 5V supply: gate voltage




4. 5V supply: VSENS.




Last one can give a false impression that 5V supply is too low, but of course the inductor's current is rising slower, because the voltage across it is lower as well. It just needs time:

5. 5V supply: VSENS with a longer pulse to allow for the core saturation to be reached.

The MOSFET appears to have a threshold voltage of 4V (or <4V?).  This could mean its almost fully _off_ at Vgs=4V.  Threshold is _not_ the on voltage, its the almost-off voltage - this is a common trap for beginners.

You need to use the full 12V supply to switch a MOSFET with a threshold of 4V.

If the MOSFET's threshold voltage was about 1 to 1.5V then 5V would be able to switch it properly.

I actually wrote "less than" 4V, so technically I wasn't wrong :). In fact it's considerably lower. I made some measurements:


Rds  Vgs
Ohm  V
>200 <2.0
137  2.0
41   2.1
13.7 2.2
4.5  2.3
1.65 2.4
309m 2.6
99m  2.8
52m  3.0
36m  3.2
26m  3.6
22m  4.0
20m  4.5
18m  10.0
17m  18.0       


(measured with a TR-1035 @1kHz square wave)

So I'd say V_th is about 3V here (or just below 2V? does it mean the conductivity threshold or a usable Rds threshold?)

There are pros and cons to both 12V and 5V.

The former allows to both use a 0.1R shunt (as opposed to a lower value) and measure higher currents while still using NMOS (I'm referring to keeping V_gs high enough even when there's a considerable voltage drop on the shunt), which are generally easier to get and cheaper for a given set of characteristics than PMOS. Faster turn-on, too. OTOH, having anything between source and ground is ugly, as was rightly said in one of the posts above.

The latter allows to power everything, both the logic and the inductor charge pulse, from the same rail, and it also makes the processes slower, allowing to use slower, cheaper and easier to obtain opamps and comparators that'll (pre)process the resulting signal, and/or extend the lower end of the measurable inductors to lower inductances.

So far a single 5V rail with a PMOS swtich sounds more attractive to me, despite the PMOS availability issues.
This is an interesting little project of dubious practical usefulness, but with a good educational potential :).

And you'd have to use a proper MOSFET driver than pulls the gate to 0.0V for off too...

True. I used the push-pull pair as one of the easiest topologies that can do the job, simply for the sake of concept proofing this thing. I don't like the gate voltage flapping around at 600 mV and the lack of making use of the higher supply voltage, when it's available, so later it'll need a proper driver. Maybe a ready-made IC, maybe I'll find something that I'll want to build myself in this good article about gate drivers from TI.

[shapirus]

That reduced slope of the gate charging curve at ~2.2V is intriguing. What is going on there? I have seen it in simulation results too, so it must be something of importance if the model creators took care to implement it.
It is apparently the point where the transistor is turning on. Something begins to work against the build-up of the gate charge at that point, and then, after a short while, that process stops, and the charging curve goes back to the shape of a regular RC charging curve.

[T3sl4co1l]

Miller plateau -- Cgd is being discharged.

Gate voltage can overshoot the Vbe bounds, because of charge storage; basically it stays turned on longer, pulling emitter up towards the supply (within Vce(sat)) even while the base voltage momentarily overshoots beyond the supply.

This is also an intuitive time-domain way to see that an emitter follower has an inductive output characteristic, and thus the amplitude increases for a capacitive load, at least at certain frequencies and impedances.

Tim