How matched are the transistors in the CD4007?
Since they are monolithic and have identical geometries, they are pretty good; I would expect offset voltages of 10s of millivolts which may not seem very good but MOSFETs do not match as well as JFETs which do not match as well as bipolar transistors. The p-channel MOSFETs do not closely match the n-channel MOSFETs however.
Two critical parameters, oxide thickness and carrier mobility, will match well on a common die. Even with these identical process parameters, matching (at the next level) depends on geometry. Looking at the metal layer die image, it appears that no special care was taken to match. The structures are serpentine (not best for matching), and not drawn identically (also adverse to matching). Obviously no attempt to common centroid (why would they?)...etc. Since the 4000 series are metal-gate CMOS, they will not give the matching performance of self-aligned Si-gate CMOS.
I designed an integrated pacemaker driver once and the company wanted to see a breadboard working (back when simulations were nascent). So, I had to actually breadboard the amplifiers etc. I did it using 4007s. Wire wrapped no less.
Maybe today, I will do a test and see how well these match. I suspect that 10s of millivolts is about right--prolly on the low side 10-20 mV though.
Oh, one more thing. Since a design does not have independent control of W/L ratios, you cannot get an optimal first-order design, so there will be some systematic offset in the 7-transistor diff amp architecture. With some gain in the diff stage, it is probably swamped by the diff pair mismatch though.
---here is an update on matching
I tested the nch devices using 135uA drain current in a diode configuration (VDS = VGS) and got the following VDS measurements:
1.588
1.600
1.594
12mV maximum spread for ONE (and only one) device.
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