Before perfboarding this (and potentially releasing the holy smoke without understanding why), I thought I'd rather ask first: could the attached design work for switching under a voltage higher than the Vds(max) of a NMOS by using two (N in the general case) in series?
If it may work only under special conditions, what are other conditions which can cause it to fail?
The expected behaviour (yes, I know the diodes will introduce a voltage drop, considering them ideal in the followings should not modify the behaviour)
a. start conditions - input LO. Q1 and Q2 non-conductive, the mid-point to a voltage half of Vcc. As a result, Q2's gate at the voltage equal with its source (D2 directly polarized).
b. the LOHI switch - Q1 goes conductive over tens/hundreds of nanosec. While mid-point voltage (=Vs for Q2) goes down, the voltage of Q2's gate lags behind with 15V - Zener D2 clamps it. So, after td(on) delay, Q1 starts conducting, after 2*td(on) Q2 starts conducting. With Q1 fully conductive, the gate of Q2 is maintained at approx 15V through D1 (compensates leakage)
c. the HILO switch - Q1 goes non-conductive over hundreds of nanosec. Once Q1's Vd(=Q2's Vs) goes over 15V, D2 becomes directly polarized and establishes a Vg=Vs, thus rendering Q2 non-conductive.
The scheme looks so simple I'm afraid I'm missing something.
Thanks in advance for comments.