As you know CMOS logic contains P and N type FETs. They connected in different, sometimes complicated chains, but the idea is (in contrast to TTL chips) that CMOS do not normally use pullups / pulldowns, but instead the turn on of high or low side mosfet. They both have some gate threshold and in the region of around middle conduct both at the same time creating a short. This wastes power, create heat and in some cases might be even damaging. That is the whole reason for having rise/fall requirements, meaning that rise/fall can not be too slow. Very slow rise/fall extends the period of time in which both mosfets conduct and create a what is called a shoot through.
You exceeded the recomended rise/fall timing not by a little, but by around 400 times.
I really do not know if that can actually kill this IC, because I never tried, I just always observe and respect the timings. Anyway, it is for you to investigate. You may even try to deliberately make it even slower and see if it kills the IC consistently.