Critique wanted for buck converter layout

[HwAoRrDk]

This my first 'serious' attempt at creating a DC-DC buck converter circuit, so I would appreciate some feedback on whether I've made a good attempt.

I want something cheap-ish, so I've chosen the Diodes Inc. AP65211A. My requirements are to take a 12V input and output 5V at up to 1A (also 3.3V 1A, for which I plan to replicate this circuit, with the exception of not repeating the input protection, and changing the voltage divider and inductor appropriately).

I've tried to minimise the loop area of input capacitors and IC as well as IC, inductor and output capacitors. Unfortunately, the part doesn't seem to lend itself to a particularly ideal layout, so the ground return path to the input caps is through some vias and the bottom layer. I've used multiple vias to try and minimise impedance.

Other things I've done - as I found them suggested in various app notes - are to avoid running the feedback trace through or near the switching path, and to remove the top ground plane underneath the inductor.

I have some queries:

• For always-on operation, the datasheet specifies that the EN input be pulled up to the input rail with a 100K resistor. I'm wondering if I can substitute it for 75K, to reuse a value from elsewhere (R5), but I note the DS doesn't "suggest" or "recommend" that 100K value, so I wonder if such a high value is required due to the EN input only accepting a maximum of 6V.
• The datasheet states "for highest efficiency, the inductor's DC resistance should be less than 20mΩ". All the inductors I can find with that spec (or lower) are physically large (more than 10x10mm) and way overkill in terms of current capability. Inductors in a more reasonable size, like 6x6mm, tend to have DC resistance more like 30-40 mohms. I'm assuming with a part like that, efficiency will be slightly lower, and power dissipation by the inductor will be slightly higher, but will there be any other effects?
• Datasheet recommends 6.8uH inductor for 5V output, but attempting to follow the calculations therein gives me a value of about 14.5uH. The datasheet also suggests a larger inductor will be more efficient at light loads. My load won't be a steady 1A, but more like a couple-hundred mA most of the time. Should I use a larger inductor value?

My plan is to assemble some examples of this small board layout so I can test before integrating the circuit into a larger design.

[gnuarm]

For lower noise, the critical high current loops should be made short, direct paths.  Interestingly enough that does not include the path to the output though the inductor.  If you give it a bit of thought that makes sense.  The point of the short paths is to minimize inductance and the output path has a major inductor in line!  So no point in minimizing that path. 

Since you have no diode but are using a synchronous part, that leaves the path from the chip through the input caps which provides the current during part of the cycle.  The loop with the input caps is important.  Presently the ground for the input caps has to run though vias across the output trace for the coil and back through vias to the chip ground.  The ground plane on the bottom is cut in the middle with traces for C4 and R4 which are not at all critical.  It might be better to reverse that with the output path from pin 2 to the coil being routed to the bottom side and back up leaving a nice wide swath for the ground from C1 and C2 to reach the chip ground pin 1.  The output path from pin 2 simply needs to be wide enough to not create a large DC voltage drop.  Even if it did, the feedback will regulate it out. 

Maybe rotate L1 90° and slide it a bit south to give C1 and C2 room to move west, closer to pins 1 and 3 where they really should be next to, especially C1.  C1 could be rotated to make it nearly on top of the U1 pins.  You just need room for a couple of vias for pin 2, one can even be under the chip possibly.  With L1 moved south and to the east that leaves room for C3 to be moved next to it and the output jack can be flipped around right next to C3.  Why no 100 nF cap next to C3 as well? 

To avoid cutting your ground plane in the middle try running Vout up and around the passives on the top of the board.  At about R1 it can via to the ground side of the board and run to the C4 via.  This won't cut the plane in half anymore.  The Vin run for R4 can do likewise.

These are gilding the lily really.  Other than cutting the ground plane in two the layout looks good.

[T3sl4co1l]

- The via above R4, cuts the top side ground plane, leaving an island below and to its right.  This island is connected by a via, so it's not floating, but it can't carry any direct current.
- Instead, move R4 via down to that location.  This greatly shortens the slot area on the back side.
- Likewise, a shorter path for C4-2 to U1-2 is preferable.  This can be routed entirely on the top side, which will remove one spoke to U1-1 and I think two GND vias (the top two between C3 and U1), which is paid for by having solid ground under U1.

- What type inductor?  Cutting out ground under it is almost always dumb, it's... silly that appnotes even quote that.  In particular, shielded types basically don't care.  Air core types are the most likely offenders, and not even for reasons that are applicable here -- namely that Q and L drop due to proximity of metal, and this not being a precision RF application, those don't matter very much (the drop might be <10%).  Q does affect efficiency, which is a good reason to use a cored type (at 500kHz, air core has much poorer Q).  And the best part, the whole issue is moot when using a shielded type, and they are readily available in this size.

- Move C3 to the, basically the exact opposite side of L1, over by D3-R3.  This reduces output loop area, and in particular, input-output area.  Filtering is best when it is point-like, so reducing the loop area between VIN, GND and VOUT improves noise.  (This is a free improvement, though it probably won't amount to much.  Additional LC sections can be added to both VIN and VOUT, extending the bottom edge as needed, to improve EMI further.)

- You may find it's worthwhile to cut some thermal spokes to U1 pads.  I've already mentioned U1-1 for another reason, and U1-3 may also prove difficult to solder.
- Also, D3-1 and R2-1 could have one spoke, and C1-C3 and D2 could have two spokes (probably the horizontal pair?).
- This doesn't matter much for reflow soldering, nor for 0805+ size chips.  It may prove helpful for hand soldering (iron), and balancing pad entry is recommended to prevent tombstoning on smaller (0603-) chips.

- EN: it's not obvious that their method is even a good idea.  The block diagram shows a protection diode (but is it also a zener, or what?) and a pulldown resistor (evidently a bit under a MΩ), and an abs. max. rating of only 6V.  A 100k pull-up will surely cause zener breakdown or something, but is this intended?  No I_EN limit is given, we must assume (nearly) zero.  So, the datasheet is contradictory.
- Anyway, threshold is reasonably precise, so it can be used for UVLO.  Preferred solution: use a voltage divider to set a minimum input voltage, probably 6-7V would be fine here.  Then at 12V supply, V_EN won't be more than 3V, nice and safe.  (And then of course you can fit whatever resistors work.  75k pulldown and 220k pullup would be alright I think.  Or, 75k up and 25k down, and then maybe R1 can be changed to 25k and R2 to 4.7k?)

- Also the 75k resistor in the first place... weird, they actually show internal compensation components.  And it's transresistance mode, i.e. the FB pin is the summing node of an inverting amplifier so input current is converted to output voltage (hence, a gain with units of resistance).  At least at AC, of course.  So, that 75k sets the input current, and so the gain (and the dominant pole, but not the zero).

The feedback network could presumably be rearranged, so that the 75k is lumped in with Thevenin(R1, R2), and the (external) zero is about 82k + C5, wired between VOUT and FB.  That is, from what's shown: R5 is shorted out; R1 and R2 are increased; and C5 has ESR added to it (really, just moving R5 over there).

That wouldn't be exactly the same transfer curve, but it would be close enough.

I guess it doesn't really matter, they just chose an unconventional equivalent.  So it looks weird, but it's actually fine.  (This isn't a recommendation, just explaining.)


- The boost network is similarly poorly documented.  No internal connection is shown to the high side driver supply, so it's just floating..?!  Obviously they must have something in there and forgot to show it.  And why show 1uF (on the application circuit) when 10nF will do?

- Efficiency and inductor DCR: well, they did say "for highest".  Compare to Rds(on) of 80/160mΩ, so, well, yeah.  Anyway, at a mere 5W output, you probably don't need every last teensy percentage point, you can afford a few tenths of a watt, it's not going to matter.

- Inductor value: Staying towards the low side, I think is probably better.  If you choose a higher value, beware that compensation values may change (R5, C5), and instability may result at high currents, regardless of compensation -- even with slope compensation, peak current mode control will only operate down to a certain ripple fraction, below which it breaks into chaotic behavior.  This operating mode isn't fatal, but acoustic noise (hiss) appears and output ripple increases; it's not preferable.


Aaand, that covers basically every possible thing.  Most of these are small, trivial changes, that take less time to do than to even read.  A spec on noise level would be nice, to determine position of bypass capacitors and whether more filtering is needed.  A better datasheet would be nice, to have design assurance of operating conditions and component values (and being able to calculate compensation would be nice).  So there may be some iteration in testing, but the starting point should be close so this won't take much time.

Tim

[HwAoRrDk]

Thanks both for the comments.

I've updated the layout with suggested changes.

The point of the short paths is to minimize inductance and the output path has a major inductor in line!  So no point in minimizing that path.

Heh, yeah, I guess that makes sense.

- What type inductor?

I'm not 100% sure yet. I don't think you can get air core SMD inductors, can you? Probably just whatever is available. One I have my eye on is described as "magnetic-resin shielded construction reduces buzz noise to ultra-low levels" in the datasheet, so I guess that means it's shielded?

Additional LC sections can be added to both VIN and VOUT, extending the bottom edge as needed, to improve EMI further.

I'll probably see what the output ripple voltage is like upon testing and then see if additional filtering on the output is warranted.

- You may find it's worthwhile to cut some thermal spokes to U1 pads.  I've already mentioned U1-1 for another reason, and U1-3 may also prove difficult to solder.
- Also, D3-1 and R2-1 could have one spoke, and C1-C3 and D2 could have two spokes (probably the horizontal pair?).
- This doesn't matter much for reflow soldering, nor for 0805+ size chips.  It may prove helpful for hand soldering (iron), and balancing pad entry is recommended to prevent tombstoning on smaller (0603-) chips.

The thermal relief spokes are all 20 mil. I've never had any problems hand-soldering parts with reliefs like this, so I think I'll just leave it all as-is in that respect.

- EN: it's not obvious that their method is even a good idea.  The block diagram shows a protection diode (but is it also a zener, or what?) and a pulldown resistor (evidently a bit under a MΩ), and an abs. max. rating of only 6V.  A 100k pull-up will surely cause zener breakdown or something, but is this intended?  No I_EN limit is given, we must assume (nearly) zero.  So, the datasheet is contradictory.

I'm guessing it must be a zener too. I suppose if it's a 6V zener, then if VIN is 12V the pull-up resistor will drop the remaining 6V and limit the current passed by the zener to 60 uA, which is nothing really. Changing the pull-up value to 75K makes it 80 uA - not much different, so probably alright?

(I assume you're basing the estimated pull-down value on the 2.85 uA I_EN @ 2V V_EN? By my calculations, that puts it around 700K.)

And why show 1uF (on the application circuit) when 10nF will do?

So you think 1 uF is unnecessarily large, and I could change it to a value that will undoubtedly be common elsewhere, like 100 nF? 1 uF is what they use on the eval board design too, so I just went with it.

- Efficiency and inductor DCR: well, they did say "for highest".  Compare to Rds(on) of 80/160mΩ, so, well, yeah.  Anyway, at a mere 5W output, you probably don't need every last teensy percentage point, you can afford a few tenths of a watt, it's not going to matter.

Ah, yes, I see. The R_DS(on) of the switching dominates - at 20 mohms the inductor's DCR is a fraction of that. Maybe I can choose a smaller size (like, 4x4 mm) and go up to DCR of 90-100 mohms?

[gnuarm]

The layout is looking good.  If you are still taking comments, I think the grounding can be improved a bit more.  I would move the Vout connector a bit closer to C3 to make room for the trace that runs to C5 to connect directly to the Vout terminal rather than being run on the back side.  Then your back side plane is less cut, but also the sense tap point is the output connector itself.  Making contact from the opposite side makes it a bit of a Kelvin connection, not that it is needed. 

The thermal break on the chip end of L1 are probably not needed.  The area of the additional copper is so low that it shouldn't make soldering harder.  The trace on the wide edge of the L1 pad toward the output is not really doing much.  I would just connect on the short edge closest to the connector. 

i would add a few more ground vias to keep the top and bottom side pours at the same voltage.

The ground for the sense circuit is the only point I see that is connected through the backside ground plane.  If you wanted, C5, R1 and R2 could be moved to the area near C3 so that R2 picks up a ground near the chip ground and also near the output ground rather than relying on the ground through the back side.  In fact, the back side ground plane could almost be removed.  If you added a jumper to connect the inductor and one for R4, you could make this board single sided and it still being every bit as good.

Of course, these are all very, very minor improvements.  I think you have a very good layout at this point. 

[T3sl4co1l]

Hmm, well putting SW on the back side certainly clears space for ground to flow around.  What I don't like about that, is it increases the exposed surface area -- more area on the switching node means more electric field emission.  So, that's another thing to look for when checking out noise performance.

Cure is simple too, by the way; scratch off some soldermask nearby, tape over the back side SW copper just in case, then solder a copper foil shield over top it.

(I think this is still unlikely to be a problem -- the last time I had a situation run afoul like this, was a SEPIC of similar size and rating, measured in an extremely sensitive near-field test, specific to automotive equipment.  The normal suite of FCC/CE tests didn't have a problem with it.  Most likely scenario I think, is if you have similarly sensitive circuitry nearby -- in which case, simply shield it and it's fine!)

Note that it doesn't actually need to be wide -- the inductor is, well, inductive, so it doesn't matter if connections to it are short and wide.  Just size it for current and you're good.

Which, honestly, the pairs of vias doesn't seem like such a bad idea, and anything narrower than a pair of vias doesn't actually save any area.

So for what it is, it's about the best it can be.  In the sense of, there might be another arrangement that does a little better, but this is a local maxima, and it's not far from the global maxima.

i would add a few more ground vias to keep the top and bottom side pours at the same voltage.

Honestly, it doesn't feel to me like more are really needed.  (You did say these are very minor improvements -- I don't disagree, basically personal opinion at this point. )

I'm not 100% sure yet. I don't think you can get air core SMD inductors, can you? Probably just whatever is available. One I have my eye on is described as "magnetic-resin shielded construction reduces buzz noise to ultra-low levels" in the datasheet, so I guess that means it's shielded?

You can -- I happen to have a kit of Coilcraft 1206CS beside me, actually.  Typical example is a ceramic core with axial winding and metallized pads on the bottom, so the value is stable, they solder just like chip resistors, and the external field is, more or less the width/height of the part.  There are also multilayer ceramic parts, which may have a vertical (thru-board) or axial field, YMMV.  Or air-core "springs", which as the name suggests, are only feasible in small values (10~100 nH?) and modest current ratings.  So if you get into a radio project or something, might be worth grabbing a kit or whatever.

But I digress -- yes, that cored inductor sounds fine.

I'm guessing it must be a zener too. I suppose if it's a 6V zener, then if VIN is 12V the pull-up resistor will drop the remaining 6V and limit the current passed by the zener to 60 uA, which is nothing really. Changing the pull-up value to 75K makes it 80 uA - not much different, so probably alright?

(I assume you're basing the estimated pull-down value on the 2.85 uA I_EN @ 2V V_EN? By my calculations, that puts it around 700K.)

Indeed, and yep.

I'd measure the pin in operation, maybe poke a few different resistors against it, confirm if that's what it is.  Different resistors just to get a better idea of the V(I) curve, and if the thing starts malfunctioning (or worse) at some current level.

So you think 1 uF is unnecessarily large, and I could change it to a value that will undoubtedly be common elsewhere, like 100 nF? 1 uF is what they use on the eval board design too, so I just went with it.

Yes -- it says minimum 10nF elsewhere.

There seems to be a tradition of using obnoxiously large caps here -- I've used the LMR14203 before, and it specifies an oddball 0.15uF.  What's more, they say that's minimum, up to 1uF.  Well, I tested it with 1nF and the waveform is a little sloppy (measuring BOOT with respect to GND -- this isn't a great measurement because I have to subtract SW from it, compounding scope errors; but given that, it still looked okay), so I put 10nF on and it's fine.

Go figure.

Interestingly, LMR14203 doesn't show any source for BOOT either (yet it doesn't require an external diode).  Yep, TI is guilty of these things too...

Ah, yes, I see. The R_DS(on) of the switching dominates - at 20 mohms the inductor's DCR is a fraction of that. Maybe I can choose a smaller size (like, 4x4 mm) and go up to DCR of 90-100 mohms?

Maybe don't go too high, but whatever is fine -- easy enough to calculate the power dissipation.  Which, 0.1 ohm at 1A is only 100mW, so it's not like it's going to be roasting alive (core loss aside).

Tim

[gnuarm]

Yeah, everything I wrote yesterday was in the noise so to speak, but adding vias to the ground layers is virtually free and probably the most significant of the lot.  The current number of vias present are so few that the rear side ground plane is doing nearly nothing from an AC perspective.  Many of the routes have to go so far to reach a via the run length using the back side plane is doubled or worse. 

I would add two vias by the ground pin on the chip for sure.  Then I would add a via close to every part connection to the ground plane.  Otherwise, why even have the back side ground plane? 

[BitsnBytes]

Where is the catch diode, if I am not wrong there should be a catch diode at the output side of the converter

Also I would like to tell that in case when you GND plane on bottom side and SMD components on top side you use via stitching to connect top SMD components to bottom GND plane. Use as much as possible as it does not have extra charges from vendor to provide low impedance return path.

Regards.

[T3sl4co1l]

It's a synchronous type, the "diode" is internal.

Tim

[gnuarm]

What Tim means is they use a second FET switch in place of the diode.  There is a brief moment when both switches are open (to avoid any overlap where input current is shorted to ground) and the inductor responds by rapidly jumping up the voltage.  But once the second FET turns on the voltage drop is lower than the diode would produce making it more efficient. 

I've read that this voltage spike produces more noise than with the diode, but I don't know for certain as I've never compared the two myself.  I know that Linear Technology (owned by Analog Devices now) has great data sheets with each one being tutorial on designing and laying out their circuits.  Check out some on their switching parts.  They have both types synchronous and non-synchronous.

[T3sl4co1l]

What really sucks is that, during the rising edge, the low-side FET turns off, so its voltage drop increases (from whatever Rds(on) gives, to a full diode drop -- the body diode carries current just like a regular diode would in this position).  This is same as described above.  But in the next instant when the high-side FET turns on, the body diode is yanked off -- hard switching, and from a very brief forward-bias.  These are the two key ingredients to generate very fast pulses by drift step recovery.

This is another point in favor of schottky diodes: they don't exhibit reverse recovery.  Not that drift step recovery would be a problem in a non-synchronous converter, as the on-time is long enough to give ordinary reverse recovery in most PN diodes.

(Sometimes you even see the recommendation to put a small schottky across the output, to fill in during the gap where the body diode would be forward-biased -- but this is almost always a poorly thought out hack.  For example the LTC3810 recommends a 1A schottky in parallel with a 10A MOSFET: the schottky has such a high voltage drop at that current, it does basically nothing.  It's not a big enough diode to serve its intended purpose, so it's just adding dead capacitance to a fast switching node.  And if you used a big enough diode, its capacitance will be so large, efficiency will suffer significantly.  The eval board for this controller emits intense several-nanosecond long impulses -- what a mess!)

It's best to have nearly zero deadtime, or even a little overlap, in synchronous converters -- if you can tune them precisely enough (within a few nanoseconds), and if you can afford some impedance in the supply (dI/dt snubber).  Unfortunately, the former isn't possible at all with integrated regulators (it's all hard wired, obviously), and is dubious to do with controllers (which may have fixed or adjustable timing, but at least you can adjust the timing at the external transistors by use of gate resistors).  The latter is probably not recommended, as the regulator's control circuitry is supplied from the same pin that draws switching current.  That is, you can't put an R||L or other snubber in series with the VIN pin without probably causing weird behavior or malfunction.  (At least, that's what I've always suspected.  I suppose I should actually try it some time, and see if some regulators handle it fine, or what.)

Tim

[gnuarm]

Wouldn't it be rather insane to add inductance to the input power path???  My understanding is this is one of the critical paths to reduce loop inductance for best operation of the circuit.  When the input FET turns on the current needs to rise from zero to the required current for the output. The reason for the high frequency input caps is to provide this fast current edge until the current starts to flow from the power source. 

Allowing overshoot of the two FETs creates a low impedance path for these fast capacitors to discharge to ground with huge ripple currents.  That just sounds wrong to me.  Solving one problem, by creating another.

[T3sl4co1l]

What's so insane about it?  Consider a current-fed inverter: if both switches turn off at the same time, voltage shoots up, limited by time delay and node capacitances.

Well, same thing here, just turned upside down.  In a voltage-fed inverter, if both switches turn on at the same time, current shoots up, limited by time delay and loop inductances.

So, you limit shoot-through (you wrote overshoot but I think you meant this, or also "negative dead time") by setting the loop inductance, simple as that.

The general takeaway is not "minimize loop inductance", but "optimize inverter impedance".  Which sounds much more sensible when stop to think about it!

There are situations where you fundamentally cannot get the loop small enough -- typically when current is very high, or devices are relatively large (both in capacitance, and in physical dimension).  In these cases, you have to work with the parasitic elements, put them in a reasonable ratio (so as to compromise between turn-on peak current and turn-off peak voltage), and add whatever damping/snubbing you can.

Another way to put it, is to consider switching loss as a function of dead time.  For large dead time, loss may be relatively high or low (hard or soft switching, capacitive or inductive load respectively).  As deadtime drops, losses may go down (due to faster switching), or up (due to forced hard switching).  There's really not much to say about this direction, because it depends so much on the load; but the interesting question is, what happens as deadtime reverses, moving below zero (overlap)?  If it goes up aggressively fast, that may be an indication that loop inductance is much lower than device capacitance, compared to load impedance.  That is, the ratio of sqrt(Lstray / Coss) to Zload.

Finally, the last thing that traditional advice is contingent on, is pi*sqrt(L*C)/2 being much smaller than the switching time.  That is, it's not going to ring if there's no energy at the resonant frequency.  This was easy enough in the days of BJTs and early MOSFETs, but isn't so easy today, especially with the archaic packages still in common use -- TO-220 and 247 typically add 7-10nH lead inductance each, and to add insult to injury, half of that (the source pin) is shared with the gate drive loop.


In present circumstances (small or integrated converters), the loop can be plenty small; the problem is, diode recovery acts like an anomalously big capacitor, so even though your loop inductance may be low (say 5 or 10nH), it may still end up being excited by switching edges.  Especially in the case of step recovery, when the switching edge can be very fast indeed (fractional ns!).

Tim

[gnuarm]

You talk about limiting the shoot through (thanks for the correction) without considering the impact that has on the abrupt change in current as required to drive the output.  The transition is from the low side switch providing the current for the output to the input providing this current, then back on the other phase.  Yeah, I guess that's not the problem I thought it would be.  In the low side switch the currents actually cancel, at least partially and if the timing is right the input spike is just a turn on.  In fact, this could reduce the EMI impact if done properly.  Not sure how to do that exactly.  I'm used to digital where circuits have widely varying delays and all design work is done with the worst case delays.  I wouldn't know where to begin designing an analog circuit to produce the "just right" overlap and shoot through without being munged up by process variations. 

I had worked on a simple circuit to switch between main power and a battery back up.  The simulation problem was shoot through back to the power input when switching to battery.  Then I realized the design was missing some large capacitors on the motor circuit.  After adding those caps I didn't care about the shoot through to the input, lol.  The caps created much larger current surges due to the voltage difference between the line and the fully charged battery.  The guy designing the board used an LT power path part and gets the same surges as in a discrete design, but he has confidence in anything LT.  The bad surges are only when the battery is connected.  As long as it doesn't blow out anything then it should be ok. 

[HwAoRrDk]

I have a further query:

The feedback resistor values the datasheet recommends for 5V output are 40.2k and 7.68k, which are (relatively) uncommon E96 series values. If I wanted to use more common values, say 43k (E24) and 8.2k (E12) - which gives 4.995V output (close enough ) - will this have any effect on the other resistor (R5, 75k) and capacitor (C5, 47pF) in the feedback network?

I am suspicious that they might need changing - particularly R5 - seeing as the datasheet seems to recommend values for all these components as a 'set'.

[T3sl4co1l]

Probably, the capacitor should be proportionally smaller, and R5 reduced by the difference in Thevenin equivalent.

Which, since neither needs to be terribly accurate (E6 say), they round to the same values.

Tim

[HwAoRrDk]

Okay, that's a relief, thanks.

And now that I look at the datasheet again, I see that the cap value doesn't actually change (either 47pF or nothing) and the 75k value is also recommended for 3.3V output with 40.2k / 13k divider resistors. So I guess it is indeed not too critical.

[gnuarm]

Okay, that's a relief, thanks.

And now that I look at the datasheet again, I see that the cap value doesn't actually change (either 47pF or nothing) and the 75k value is also recommended for 3.3V output with 40.2k / 13k divider resistors. So I guess it is indeed not too critical.

I don't recall seeing the series resistor on the feedback input in other designs.  Not sure what it is doing.  In fact, any current into or out of that pin creates a bias voltage across the resistor that will disturb the accuracy of the circuit.  The Thevenin equivalent resistance is a limitation to the size of the resistors you can use the the feed back divider because of this bias.  It doesn't makes sense to me to add resistance here.  I suppose it is part of the stabilization.

The capacitor is to improve the circuit response and make it more stable.  47 pF is not far from nothing actually.  An 0603 resistor pad over a ground plane is about 0.3 pF, so the four pads at the common node is 1.2 pF alone, not counting the trace.  In fact it is not entirely uncommon to construct low value capacitors from circuit board traces or areas.  That is the function of having ground and power plane opposite.  This is also the reason why ground plane is removed opposite feedback nodes in very high speed op amp circuits. 

The reference talks about the feed forward capacitor a bit.
https://www.ti.com/lit/an/sbva042/sbva042.pdf?ts=1612630499626

[HwAoRrDk]

I suppose it is part of the stabilization.

Yeah, the datasheet says: "A serial resistor RT is also recommended for improving the system stability, especially for low VOUT (<3.3V)."

[HwAoRrDk]

Of course, just as I get back to this thing, I discover that the AP65211A is now obsoleted and "not recommended for new designs".

The replacement part is the AP62200. Seems it has some improvements over the old part: 750kHz switching frequency, built-in pull-up current source on EN pin, and some slightly different switching modes for better low-load efficiency.

I've revised the design of my little test board. Any comments on this new layout appreciated!

Some notes:

- No external pull-up to VIN rail needed for EN pin. Leaving it floating means it will automatically start up (and with default UVLO level).
- Seems no additional compensation parts are recommended on the feedback network (i.e. 75K and 47pF), so I removed them.
- Recommendation is for 2x 22uF output caps in parallel, so I did that too.
- Inductor changed to 4.7uH, as that is what is now recommended for 5V output. Incidentally, re-running the same calculations for L value myself as before comes out with 4.86uH, which is more comforting that the number agree with their value. Could probably use a physically smaller part now (due to higher switching frequency), but I think I'll leave it as-is as at least it'll have low DCR.
- Recommendation is only for 100nF bootstrap cap (and eval board uses that too), so I changed it from 1uF.

[gnuarm]

Why roll your own converter rather than use a module?  There are companies that make very tiny modules that do the job of your board. 

I designed a test fixture for a product intended to be powered by on board regulators by national.  When they didn't work I found the data sheet was missing a limitation that was only on the web page.  For some time I powered the unit with an external multi-output supply that was large and clunky.  Then I found TO-220 size modules that encapsulated an entire switching circuit.  Some relatively minor mods to the boards allowed these switchers to be added allowing me to replace the clunky supply with a single wall wart.  I'm still using that test fixture 13 years later.

Since then Enpirion started up making surface mount chips that incorporate the inductor forming a complete switcher minus the power caps.  I believe they were bought by Intel and are found on many of Intel's products. 

Würth Elektronik has a line of very small modules.  They have a video presentation at Digikey. 
https://www.we-online.com/web/en/electronic_components/extra_pbs/webinars/webinars_midcom/2021_webinars/March2021_Micromodules1.php?utm_source=emailus&utm_medium=emailus&utm_campaign=march21_powermodules2webinar_da

And information here
https://www.we-online.com/catalog/en/pm

Design is fun, but power supplies don't require an entire circuit to be designed anymore.  Modules can be easy.  Just a thought.

[HwAoRrDk]

I'm not specifically trying to design a standalone module or breakout here - this small board is just for experimentation. The idea is to get it right here before I go putting the same design in to a larger project.

Also, off-the-shelf modules are expensive, and most of them don't seem to supply more than 1A.

[gnuarm]

What are your requirements?