silicon photolithography

[carl0s]

I understand how silicon dies are made from wafers, the photolithography stuff, the crystal drawing, lead wires, packaging etc.. but all the nice vid-jeos I've watched seem to skip over the subject of how a 'picture' on a piece of silicon can be the difference between all the various electronic components. Is it just down to the shape/pattern that is put on the silicon? does current just jump gaps and shapes differently or something?

oh, there is that N/P doping thing that I've tried to read about but still don't understand. Is that key to it?

I've just ordered some bare dies to look at under the microscope. It would be nice to get a deeper understanding of what is what, based on appearance. I understand some are masked, and they are multi layered too (ouch).

[carl0s]

Every time we do lithography, we want to mask something. Once some parts are masked, we can pattern the exposed rest with etching, ion implanting, deposition or other processes.
Then, the mask is removed, leaving the remaining pattern after processing. This process is repeated to build up layers in an IC.

So the lithography is just providing the mask for the next layer, which could be ion implanting, deposition (that's the n or p doping that I will try again to read and understand?), and/or other processes ?

So basically there's a lots of 'other processes' that the vidjeos I have been watch just skipped over?

[carl0s]

I was hoping I might be the first to attempt to make a silicon chip (one or two transistors ?) at home, some time in the next 20 years (time to retire... would anybody else be bothering?)

Anyway I came across this, so I'm well behind. Nice. I shall just follow:

[james_s]

About 10 years ago I went to the bay area maker faire and saw Jeri Ellesworth demonstrating some simple ICs she made at home so I'm afraid you're a bit too late to that party. It's still a rather exclusive club though.

[T3sl4co1l]

AFAIK, Jeri and Sam are the only two on the internet who have succeeded.

The comment about "does current just jump gaps and shapes differently or something?" is kinda-sorta right, when the current is in a semiconductor.  Over small enough distance scales (< 10um or so in Si), the charge carriers diffuse about and anywhere they get sucked into a junction, you have a current flow.  When this is done over a short distance (~1um) between junctions, and over a wide area (a flat diffusion), it turns out most of the current drawn from the thin (~1um) layer actually diffuses straight on through to the other junction.  Whammo, you've got a BJT.

BJTs are as important for their unintentional behavior, too -- in logic devices, ESD diodes typically have some current gain between neighboring pins, or to VDD or VSS.  This is usually pretty small (I've found the hFE of parasitic transistors in the 74HC family is typically ~0.5 to VDD and ~0.03 between adjacent pins -- low, but nonzero!), but the pairings can still be triggered into SCR latchup (at >100mA for 74HC).

MOSFETs are, I think, less mysterious, in that the channel starts depleted or reverse-biased and a minute surface layer (~100nm) is teased into being conductive by an applied electric field.  When this surface layer is applied between two diffusions, whammo, they conduct!  They're also easier to make in some respects (fewer steps, and less fiddly?), but also harder in others (high purity is required to avoid surface states and mobile ions trapped in oxides).

Tim

[MosherIV]

but all the nice vid-jeos I've watched seem to skip over the subject of how a 'picture' on a piece of silicon can be the difference between all the various electronic components. Is it just down to the shape/pattern that is put on the silicon? does current just jump gaps and shapes differently or something?

oh, there is that N/P doping thing that I've tried to read about but still don't understand. Is that key to it?

First, the only components that can be formed are: tracks, junctions ie diodes or transistor and capacitors.
The shapes are usually a trade secret for the latest geometry size, you may be able to find information about the shapes from long abandoned geometry sizes. I was certainly shown some of the shapes they used back in the 80s when I was at university.

As I said, one of the components you can form is Tracks to carry current around the silicone circuit.
The deposition process has been adapted to lay copper in the last decade, previously you could only lay aluminium. This is used for tracks. Can also be used for heat conduction. I beleive tha latest trend is to use copper to form 3d shapes for stacking substrates.

N/P dopping, you need to have N (negative - has loose electrons) and P (positive - has shortage of positron) to be able to make silicone junction ie N/P junction ie a diode. Add another junction to make a transistor.

[carl0s]

Thanks everybody, this is really interesting.
The comment about what can/can't be put down is interesting. I did once read that putting resistors inside ICs was 'very expensive' or something. Perhaps that explains why some of the small transceiver ICs I've done stuff with (e.g. ST L9637D) have to have just a single resistor added for the reference design.

[T3sl4co1l]

Yeah, traditional resistors are either made from doped semiconductor (which has modest resistivity, making reasonable values practical), either by thin necked diffusions (almost JFETs) or by long sinuous, average width tracks; or in actual resistive material (CrSi most often I think?) as a separate layer.

Diffusion is rather crude -- it depends closely on the dopant concentration and annealing time.  The tolerance of a diffusion resistor might be -30/+50% or worse; but the resistors will be reasonably well matched between each other (better than 10%?).

Deposited resistors are quite good, I can't remember if I've read how good they are for initial tolerance.  They are often laser trimmed, which means they have to be the final metal layer, on top of the existing metal layer.  (Can't cheat by using it for the lone metal layer, even if you can handle the added resistance -- it can't be deposited on silicon because transition metals play dirty with silicon's bandgap.)

Metallization (aluminum or copper) isn't practical to use, as the resistivity is too low, even if the thickness is kept low.  Would be practical for thin-film resistors on macroscale, but down on a chip, it just won't work out.

That's actually kind of a lie; obviously the point is, metallization would only practical for low resistances -- which you can actually see examples of, in power transistors like the outputs in TL431 and LM317 and etc.  The power transistor is made of many BJT cells, connected in parallel through relatively long emitter contacts.  The resistances tend to ballast the parallel array, improving current balance and SOA.

Probably worth noting that, just like copper on the PCB, the tempco is terrible, so while you can use it for small resistances, don't count on it being all that suitable.  (The ratio of resistivity to inductivity of copper is also pretty poor on the PCB scale, making it even worse for "resistors" at AC!)

Tim