Should Main Ground Layer Cover Entire PCB to Reduce EMI with Isolated DC-DC?

[Dele]

I’m designing a 4-layer PCB, which includes several galvanically isolated DC-DC converters that power separate subsystems located at different parts of the board. Each subsystem with its own power supply has its own independent ground planes.

Should the main ground layer (the ground from the main power source) be filled across the entire board, so that the isolated ground islands are placed above this main ground layer throughout the board?

There’s a reference from TI https://www.ti.com/lit/an/slla368c/slla368c.pdf, (Figure 9. 3-D Diagram of PCB Layers With Interlayer Stitching Capacitance) which suggests that this should be done to increase capacitive coupling and ensure low impedance for noise from the DC-DC converters, in addition to a Y2 capacitor. On the other hand, some manufacturers of similar chips recommend leaving empty space under them on all layers.

I think it’s necessary for reducing EMI; what do you think?

[T3sl4co1l]

No.  When making a slot between planes, commit to it.

Presumably, that isolation is required for high voltage reasons (some kV surge immunity?), and good luck achieving enough creepage and clearance with ground underneath it, while also using vias and thru-pads in the usual way.  Or, put another way: with design rules set up properly, go right ahead, almost nothing will be able to fill anyway.  Or, maybe you could pull it off, maybe the isolation requirement is more modest in the design, no idea, but there is another (if less strong) reason: might as well keep capacitance low, so that you can control total capacitance by way of "Y" caps.

Handle CM EMI with traditional means: minimize DC-DC capacitance if possible; add Y-cap; CMC and another Y-cap if necessary; if application can't tolerate much if any C (e.g. gate driver), don't bother, and find other means to solve EMI.

EMI might also be irrelevant anyway: for the gate drive example, they're already swinging at 100s of V -- your EMI filtering belongs elsewhere -- namely, prevent it going up the mains input, and thoroughly (RF) ground the main board so the EMI current across the DC-DCs' capacitance can be sunk effectively.

There's dozens (hundreds?) of possible applications that fit your outline, so I cannot possibly say which set of solutions applies; I don't even know what if any EMI concerns (converter emissions, required equipment level, and how energy is coupled from the one to the other) you actually have; for all I know, this is just a generic concern and not actually motivated by any requirement at all.

Tim

[Doctorandus_P]

Many SMPS circuits have a high voltage capacitor between the primary and secondary side to filter EMI, and you could use the GND plane as such a capacitor too, but that is not the primary purpose of the GND plane. The main purpose of the GND plane is to provide the lowest impedance path for return currents, and for that, the local GND plane has to be connected to the actual "GND" pins of all parts that have these GND pins.

Because I noticed a conflict between my knowledge and your claim of the Ti document, I had a look at it, and they do it right, and not the way you wrote it. They use separate GND planes for the primary and secondary side (So each has it's local GND plane to connect the parts to), but they overlap the GND planes near the "isolation barrier" to also form this EMI filter cap in the PCB itself. Look carefully at the provided pictures in slla368c.pdf.

[Dele]

Okay, I understand that placing the main ground under the local isolated ground might be a bad idea.

For example, take the TDA51S485HC chip, which has a built-in DC-DC and an RS485 transceiver. If we consider the area under the chip, the top layer will be empty, followed by its local ground, which will be limited in size approximately to the width of the chip. What should be done next, if we are not creating capacitive coupling? Should the subsequent layers remain with gaps? That’s also not great, as it essentially creates cuts in the main ground...

[PGPG]

20 years ago I was designing isolated RS485 knowing not a lot about EMC. I wanted to have as high isolation voltage as possible. To convert power I used MAX845 as generator and I found trafo having 4kV and (if remember well) 4.2pF in-out capacitance. I have made connection (+ and -) to MAX485 and the rectified output (+ and -) voltage through 1k ferrite beads to limit high frequency disturbances generated by DCDC.  To isolate signals I used one of ADuM isolators. This 2 layer board solution (without capacitor blocking GNDs between both sides and with both GNDs as far away from one to another as possible) passed EMC tests. I think that mainly thanks to relatively small DCDC frequency (don't remember) and small trafo capacitance and ferrite beads.

Later (but long ago - may be 2010) I read that there are new serie something like Power ADuM containing also internally in IC DCDC with integrated high frequency trafo (I suppose without core) working at close to GHz frequency. I understood that this solution without capacitance made by overlapping GND layers can't pass EMC tests and even with it it is close to not pass. I have never tried to use it and don't plan to use it ever.

I don't know anything more in this subject.

[Dele]

Yes, these are conflicting approaches. On one hand, controlling capacitance is better left to a controlled Y2 capacitor value. On the other hand, leaving gaps in all layers under the chip is also not ideal, as it results in cuts in the main ground, and making cuts in the ground is generally bad.