Reasonable (and necessary) metods of protecting MOSFET gates?

[shapirus]

I have the experience of killing small MOSFETs such as 2n7000 used (in my projects) without any protection of the gates, which were connected directly to something user-controlled, such as button, or an external voltage, especially during development, when it is possible to touch bare wires connected directly to the gate. Damaging factors in my case were (potentially) ESD and mains-induced interference coming via capacitive (as far as I understand) coupling between the windings of a transformer-based PSU.

To prevent this kind of damage, I started to use the following method of protection which I learned from the various IC datasheets where it is known as input clamping diodes:



Pros:

1) this method works: I've never killed a transistor protected this way;
2) any sufficiently fast off-the-shelf diode can be used, no need to obtain TVS diodes rated for a specific voltage.

Cons:

1) I'm not sure if this method uses the least possible number of parts;
2) I'm not sure if the statement in the second advantage above is definitely true.

Now, drawing parallels between software and electronics engineering, in the former you always want to validate user's input to prevent any kind of unexpected behavior of your program caused by input values falling outside of the allowed range.

On the other hand, when you pass internally generated data between subroutines inside the program, you (as long as the program is properly designed) don't need to worry about validating it on the receiving side.

Does the same apply to electronics, in particular, protecting MOSFET gates? For example, when a gate is driven directly from an output of an IC such as 4017 or 4520, what do we need to protect it against? I guess in this case it's the question of whether we care about ESD protection (e.g., when someone touches the board removed from the device's housing) and whether this protection is implemented (not necessarily as such -- might be a result of something else) in the driving device's output.

What's the sane approach here that is both valid and required for practical application without going paranoid?

[JJ_023]

Have you looked into utilizing a gate driver?

[shapirus]

Have you looked into utilizing a gate driver?

Yes. They are generally too expensive and scarce where I live. I can justify using them for driving beefy transistors with high Cgs from logic ICs that can't properly drive them directly, which is their primary purpose. However, using them to drive something like 2n7000 is a different story. Besides, it's a hobby for me, which means having fun, and I have more fun building things from discrete components wherever it stays reasonable enough. Also, I'm trying to learn what the reasonable general approach to this is, rather than finding a solution for a specific project.

That aside, speaking of gate drivers, I take it that they can be used to handle (aka sanitize/validate) user input such as coming from a button, or a voltage source, because they, I believe, should have integrated input protection (not sure if that's a general rule though -- I checked a couple datasheets and found no definitive answer). That's a good suggestion.

[radar_macgyver]

The diodes provide a path for static charge to dissipate to ground or Vdd. You could achieve the same with a resistor too, value selected to minimize parasitic power consumption. If the lower diode (gate to ground) is a TVS or zener, you get the added benefit of limiting Vgs to avoid puncturing the gate of the FET.

In terms of what to protect against, it depends on what's between the FET and the driving IC. If it's all on the same board with short traces, then the only reasonable way EMI or static can couple into the gate is if the board is handled. If there's a long enough wire between the two, you could pick up EMI. Also, the higher inductance could end up resonating with Cgs and ringing, but this is usually only a problem for larger FETs with high Cgs.

The software analogy only works fully when one considers every component in a design, including the parasitics. In the example above, that would be the inductance of the conductor from the driver IC to the FET gate.

[wraper]

You should not use 2n7000 for anything user accessible to begin with. Even their safe handling during assembly is an issue. And it working after assembly does not necessarily mean it didn't get wounded.

[langwadt]

most IC have something similar on every input

keep in mind you schematic will only limit the gate Vgs to VDD, which could be quite a bit higher than allowed Vgs

[shapirus]

keep in mind you schematic will only limit the gate Vgs to VDD, which could be quite a bit higher than allowed Vgs

Yes that's a good point. I should have mentioned that I assumed low-voltage circuits, meaning sub-20V supply, which covers most generic transistors (but need to keep in mind that there are many low-Vth ones that have even lower max allowed Vgs, for which the caveat should be adapted accordingly).

[shapirus]

You should not use 2n7000 for anything user accessible to begin with. Even their safe handling during assembly is an issue. And it working after assembly does not necessarily mean it didn't get wounded.

Well yes, they are quite fragile in this regard. However, as I mentioned, since I started to use the two-diode input protection method shown above, I have not damaged any of them, or at least not damaged to such a degree that I could measure.

Suppose we need to provide the user with a momentary switch (button) to power on a subcircuit via a small P-channel MOSFET acting as a switch, whatever the reason might be to use a transistor instead of the button itself. Latched power-on can be one of examples.

My first idea of how to do this would be to pull the gate up to VDD via a resistor and wire the button so that, when pressed, it shorts the path between the gate and GND. After a few dead transistors, I began to add those two diodes to provide short paths from/to GND and VDD for whatever unwanted charge may come to or from the gate pin, and that seems to have worked well.

Is that a bad idea? What would the right way of doing it be?

[Peabody]

My first idea of how to do this would be to pull the gate up to VDD via a resistor and wire the button so that, when pressed, it shorts the path between the gate and GND. After a few dead transistors, I began to add those two diodes to provide short paths from/to GND and VDD for whatever unwanted charge may come to or from the gate pin, and that seems to have worked well.

I don't see what would cause damage to the mosfet in that situation.  The gate/source voltage of the 2N7000 is +/- 20V.  Are there any inductors in that setup?

[Manul]

Suppose we need to provide the user with a momentary switch (button) to power on a subcircuit via a small P-channel MOSFET acting as a switch, whatever the reason might be to use a transistor instead of the button itself. Latched power-on can be one of examples.

My first idea of how to do this would be to pull the gate up to VDD via a resistor and wire the button so that, when pressed, it shorts the path between the gate and GND. After a few dead transistors, I began to add those two diodes to provide short paths from/to GND and VDD for whatever unwanted charge may come to or from the gate pin, and that seems to have worked well.

Is that a bad idea? What would the right way of doing it be?

The idea is ok. Just a few notes. I often see, that people add clamping devices, but don't include any current limitting (series resistance). It might be ok in some cases, but not always.

One thing is that without current limitting clamping device (for ex. diode, TVS) might get overloaded. In such case, clamping voltage may exceed the expected value or the clamping device might simply fail.

Another thing is the speed of clamping. That speed is the speed of clamping device itself plus (very important!) the full physical path of clamped current. Every lead and every trace has parasitic inductance and the clamping path might be quite long, depends on layout. So all that inductance also delays the clamping action, especially if no current limitting is used. ESD spikes might have nanosecond rise times. So one needs to make clamping paths short. Again, current limitting helps. Added extra capacitance also helps (essentially makes RC low pass filter) to attenuate fast edges.

One last note, if you use buttons and switches, don't use very high value pull-up resistors. Switches require some wetting current to work reliably. So for example 100k is probably not a good pullup. Target at least 0.1 - 1mA of current. For some switches even more. In some designs which include RC filter, capacitor discharge supplies momentary wetting current and pull-up then can be of higher value.

[Thunderer]

The most used protection for mosfets gates is a zener diode. Of course, the zener voltage will have to be few volts lower than the maximum Vgs voltage.

A 20V Vgs mosfet can be protected with a 12V zener.

The same for P and N channel.





In the case of simple diodes, like your sketches (the one between the G and the S) how much voltage you think it will ever reach the gate?

[Jwillis]

Lets not worry about whether or not it's a good or bad idea. Lets analysis your circuit and choices of components.
This is what we know.

"ESD destruction of the MOSFET occurs when the gate-to-source voltage is high enough to arc across the gate dielectric. This burns a microscopic hole in the gate oxide which permanently destroys the device."

The 2n700 has a maximum Vds of 60V and a maximum. The potential voltage difference between the drain and source cannot exceed 60V.
The Vgs is plus or minus 20V. The potential voltage difference between the gate and source cannot exceed plus or minus 20V.
Obvious.
The 1n4148 has a forward voltage of 500 to 600mV . But for the sake of simplicity lets say it's 0.7V
The reverse breakdown voltage is 75V.

In your circuit, D3 will not pass any voltage unless the gate voltage plus the forward voltage(0.7V) of the 1N4148 is higher then the drain voltage. That's good because we want the transients to be shunted away from the gate right. As long as those transients don't exceed the potential voltage difference  of plus or minus 20V between the gate and source.

D4 won't do anything for the gate unless the reverse breakdown voltage of the 1N4148 exceeds 75V. That will exceed the maximum potential difference of 20V for Vgs. Good bye Mosfet.

So if you want to suppress transients at your gate that will exceed the Vgs, Then reverse breakdown voltage of D4 has to be 20V or less. And that diode must be able pass that voltage in nanoseconds to be effective. This is why a TVS is used because that's what they are designed to do.

[David Hess]

Two diodes works fine if the supply voltage is below the maximum gate voltage.  Otherwise a zener or TVS diode is a better choice.

An input RC filter can also work to protect against ESD.

[shapirus]

In the case of simple diodes, like your sketches (the one between the G and the S) how much voltage you think it will ever reach the gate?

VDD + (roughly)0.5V / GND - 0.5 V, in the ideal case. If we consider the parasitics, then I don't know. It's for the unwanted voltage such as ESD and EMI-induced, of course. For the gate controlling voltage, it's usually VDD, as most of my circuits are powered by 12V.

That's why this kind of protection is only suitable where VDD and GND don't exceed or fall below max/min Vgs. Otherwise, as mentioned in the post above, a Zener or TVS will be a better choice.

[shapirus]

D4 won't do anything for the gate unless the reverse breakdown voltage of the 1N4148 exceeds 75V. That will exceed the maximum potential difference of 20V for Vgs. Good bye Mosfet.

The purpose of D4 is to provide a short path from GND when the gate potential falls below GND (minus the junction drop). D3 is for providing a short path to VDD when the gate potential exceeds VDD plus the junction drop.

This method requires that something else between the VDD and GND rails is able to sink the charge deviated from the gate by the diodes, but this applies to other methods with TVS and Zeners too, I think. For simple cases, my guess would be that it will be handled just fine by the ICs' decoupling caps and other passives (and the ICs themselves).

It's a different story when a low-impedance high-voltage source is connected to the gate. Then the respective rail will see almost all of it, which will burn something, or all, on the rest of the circuit. This is where, as rightly mentioned above, an input RC filter will save the device by limiting the input current and dropping the excess voltage on the resistor, whose value must be calculated with respect to the max expected input overvoltage and power consumption of the rest of the circuit.

As I mentioned, I learned this two-diode type of input protection from the IC datasheets. However it took me quite a while to realize what the "Input clamping current" in the absolute maximum ratings actually was. Surely enough, it was the max allowed current for the clamping diodes. And that value allows to calculate the required value of the resistor to be placed in series with the input pin.

And that diode must be able pass that voltage in nanoseconds to be effective. This is why a TVS is used because that's what they are designed to do.

1N4148 are in the "fast" category, whatever that means (what does it mean btw, besides a low reverse recovery time -- or is that all we care about?)
Whether they are fast enough to conduct the ESD charge before it makes it to the gate, I am not sure, but it's something that is possible to test practically (for a qualitative estimate, i.e., can we kill a transistor with such protection by an ESD spark). An RC filter before the diodes will (will it really?) reduce the requirements for the speed of the diodes.

[T3sl4co1l]

I haven't damaged any 2N7000s, I think, although I don't use many compared to 2N3904 and such (let alone SMTs).  I probably would have damaged a few over the years if I did, particularly in the early ears.

Understanding how to handle components and avoid ESD is more important, I would say.  Static builds only when you move around, and it's static discharge that kills.  Discharge to, much of anything really -- the resulting EMP burst is quite fast-rising and induces into everything nearby, but especially direct hits, of course.  The peak current can be 10s of A, for mere 10s of ns, but this is more than enough to damage microscopic semiconductor structures; literally blow them up, material gets displaced, removed, vaporized in the process.

Working on a mildly conductive (static dissipative) surface helps greatly, and even without, one can practice safely by grounding to the circuit/equipment being worked on.  So, say you're building a PC, just every time you reach inside, remember to touch your body to the metal enclosure, and you'll be safe at least until you shift your position (beware shifting in your chair, idly suffling your feet, etc.).

You don't need to be galvanically grounded, but it does serve as a universal reference, and all you need then is to tie equipment to the same ground, and everything's unipotential.  This is the industrial grade solution: make floors and workbenches mildly conductive, make personnel mildly conductive usually by shoe and wrist straps, and occasionally straps for the equipment itself.  Tools can be grounded (e.g. soldering iron's metal housing), at least with a large resistor (again, mild conductivity, all that's needed to address ESD; some resistance to an iron might be a good thing in case the equipment you're working on isn't completely discharged, or off even(!)).

So, for breadboarding, just touching the power supply, or ground wire, or scope probe clip, or whatever, every once in a while, suffices.

Tim

[David Hess]

And that diode must be able pass that voltage in nanoseconds to be effective. This is why a TVS is used because that's what they are designed to do.

1N4148 are in the "fast" category, whatever that means (what does it mean btw, besides a low reverse recovery time -- or is that all we care about?)
Whether they are fast enough to conduct the ESD charge before it makes it to the gate, I am not sure, but it's something that is possible to test practically (for a qualitative estimate, i.e., can we kill a transistor with such protection by an ESD spark). An RC filter before the diodes will (will it really?) reduce the requirements for the speed of the diodes.

Diode speed almost always refers to reverse recovery time which is irrelevant here.  What we want is forward recovery time however this is rarely specified and almost all diodes are fast in this respect unless they are defective.

An RC filter makes a big difference not because of the speed reduction but because the capacitance absorbs most of the charge, reducing the peak voltage.  For the same reason large MOSFETs which have 1000s of picofarads of gate capacitance are also resistant to ESD.

[Thunderer]

In the case of simple diodes, like your sketches (the one between the G and the S) how much voltage you think it will ever reach the gate?

VDD + (roughly)0.5V / GND - 0.5 V, in the ideal case. If we consider the parasitics, then I don't know. It's for the unwanted voltage such as ESD and EMI-induced, of course. For the gate controlling voltage, it's usually VDD, as most of my circuits are powered by 12V.

That's why this kind of protection is only suitable where VDD and GND don't exceed or fall below max/min Vgs. Otherwise, as mentioned in the post above, a Zener or TVS will be a better choice.

When I made the comment wanted to make you realize that if the 12V is lower than the Vgs you are good to go, otherwise not. You clearly got that right!

[shapirus]

An RC filter makes a big difference not because of the speed reduction but because the capacitance absorbs most of the charge, reducing the peak voltage.  For the same reason large MOSFETs which have 1000s of picofarads of gate capacitance are also resistant to ESD.

Yes, that applies when charge is low, but its potential is high, which is usually the case with ESD: the charge is so small that it won't cause a significant voltage increase when it's absorbed by the higher capacity of the RC filter or Ciss of a larger transistor.

What I meant with regards to the speed of the diodes, was for the case when that charge is sufficient (including infinite -- when a voltage source is connected) to fully charge the capacitor in the RC filter and allow the gate potential to grow further. In that case, the RC filter will serve as a low-pass filter, effectively smoothing, or stretching in time, the leading edge of the charge pulse, providing more time for the diode to turn on and begin conducting to/from VDD or GND.

Not sure if completely correct, but that's my understanding.