Ok, an even further update, I am sort of spamming this with reply's :S
I have managed to get an output with this code:
// This is the Verilog Code for a 4026 Decade Counter, complete with all of it's functionality including enables, etc.
// This shall be a work in progress as I learn more about verilog code, eventually this should end in some highly efficient Verilog code,
// as I become more profficient with the language.
// Creating Initial Module
module ic (clock, reset, enable, a, b, c, d, e, f, g);
// Defining Input and Output Ports
input clock, reset, enable;
output a, b, c, d, e, f, g;
// Defining Port Types
reg a, b, c, d, e, f, g;
// Creating Tracking Variables
reg [3:0] counter, counter_n;
// Main behavoural code
always @ (posedge clock) begin
if (counter == 4'b0000) begin
a = 1; b = 1; c = 1; d = 1; e = 1; f = 1; g = 0;
end
if (counter == 4'b0001) begin
a = 0; b = 1; c = 1; d = 0; e = 0; f = 0; g = 0;
end
if (counter == 4'b0010) begin
a = 1; b = 1; c = 0; d = 1; e = 1; f = 0; g = 1;
end
if (counter == 4'b0011) begin
a = 1; b = 1; c = 1; d = 1; e = 0; f = 0; g = 1;
end
if (counter == 4'b0100) begin
a = 0; b = 1; c = 1; d = 0; e = 0; f = 1; g = 1;
end
if (counter == 4'b0101) begin
a = 1; b = 0; c = 1; d = 1; e = 0; f = 1; g = 1;
end else if (counter == 4'b0110) begin
a = 1; b = 0; c = 1; d = 1; e = 1; f = 1; g = 1;
end
if (counter == 4'b0111) begin
a = 1; b = 1; c = 1; d = 0; e = 0; f = 0; g = 0;
end
if (counter == 4'b1000) begin
a = 1; b = 1; c = 1; d = 1; e = 1; f = 1; g = 1;
end
if (counter == 4'b1010) begin
counter <= 0;
end
else begin
a = 1; b = 1; c = 1; d = 1; e = 0; f = 1; g = 1;
end
if (reset == 1'b1) begin
counter <= 4'b000;
end
if (enable == 1'b1) begin
counter_n <= counter + 1'b1;
end
counter <= counter_n;
end
endmodule
// Testbench code beginning here
module ic_tb;
reg clock, reset, enable;
wire a, b, c, d, e, f, g;
ic ic_1 (.clock(clock), .reset(reset), .enable(enable), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g));
initial begin
$monitor ("clock=%b, reset=%b, enable=%b, a=%b, b=%b, c=%b, d=%b, e=%b, f=%b, g=%b", clock, reset, enable, a, b, c, d, e, f, g);
clock = 0;
reset = 0;
enable = 0;
#5 reset = 1;
#10 reset = 0;
enable = 1;
#10;
#10;
#10;
#10;
#10 $finish;
end
always begin
#5 clock = !clock;
end
endmodule
However it is a constant output from the else statement at the end of the behavioral code! I still don't know what I am doing wrong!
Here is the output for reference:
clock=0, reset=0, enable=0, a=x, b=x, c=x, d=x, e=x, f=x, g=x
clock=1, reset=1, enable=0, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=1, enable=0, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=1, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=1, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=1, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=1, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=1, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
clock=0, reset=0, enable=1, a=1, b=1, c=1, d=1, e=0, f=1, g=1
$finish called from file "design.sv", line 83.
$finish at simulation time 65
V C S S i m u l a t i o n R e p o r t
Time: 65 ns
CPU Time: 0.240 seconds; Data structure size: 0.0Mb
Tue Jan 19 20:54:50 2016
Done
Once again thanks for any help in advance!