Reading schematics that don't show inputs explicitly?

[mindcrime]

Sometimes when browsing online tutorials, or datasheets (test circuits), etc., you'll find a schematic that does not explicitly label the input(s) of the circuit.  See, for example, Figure 5.1.3 on this page:

http://www.learnabout-electronics.org/Digital/dig51.php



I assume that they don't show these because it's supposed to be so obvious that there's no need to label those points explicitly... but this bothers me on a fundamental level. Maybe it's just a mindset thing, but I always favor "explicit over implicit" and I don't like trusting things to faith, or common lore, or hunches, etc.  And so when I see one of these, I generally just move on, as I'm not interested in trying to infer what the schematic author was trying to say (but couldn't be arsed to actually say).

That said, it's so common that I guess I have to suck it up and deal with it. So what's the big secret? How do you know where to apply voltage on something like this? And likewise for other "no explicit inputs called out" type schematics?

[Whales]

For that particular example you need to take it literally: this circuit does not have an input.  It oscillates on its own (like a cold human ).  Not all circuits have an input, unless you count their power pin (ie turning them on).

(On a more general note: yes assumptions by people writing technical works can get really annoying, especially when people give you funny looks for asking.  I've been told before "you should go back to school!" and such things, the urge to murder has been strong.)

[fourfathom]

Yes, this one has no input, it's an oscillator -- output only.  With this schematic if you want to build it you are supposed to look up the 74HCT04 and find the input, output, ground, and power pins.  You will need to know that you should terminate unused input pins to power or ground (there will be four unused inputs.)  You will need to figure out what type of crystal is appropriate (not all xtals will work in this circuit.)  But this schematic is really supposed to be an example, not necessarily a construction project.

[mindcrime]

For that particular example you need to take it literally: this circuit does not have an input.  It oscillates on its own (like a cold human ).  Not all circuits have an input, unless you count their power pin (ie turning them on).

Right, that I get. I don't mean a "signal input" necessarily... I'm including the power (Vcc) as an "input" in this context. And this particular example doesn't even show where that goes. I'm assuming you just apply the power to the base of IC1a because I don't see how it makes sense otherwise, but it's frustrating that they don't tell you so definitively. :-(

[mindcrime]

Yes, this one has no input, it's an oscillator -- output only.  With this schematic if you want to build it you are supposed to look up the 74HCT04 and find the input, output, ground, and power pins.  You will need to know that you should terminate unused input pins to power or ground (there will be four unused inputs.)

That's a good point. Since they do call out the specific IC, it makes sense that they're basically "incorporating by reference" it's datasheet.  Somehow that flew completely over my head when I first glanced at this.

[rstofer]

I'm not surprised that Vcc and Gnd are simply implied.  That's pretty common practice.  The circuit itself is demonstrating how to create an oscillator and details like Vcc and Gnd are not that important.  A glance at the datasheet will disclose the requirement.

Once you have seen it a few times, it's no big deal.

[Jwillis]

The component symbol is that of an inverter or NOT gate. Theirs no other input drawn in because its not a representation of an operation amp.This just simplifies the drawing by omitting redundant circuitry.

[mindcrime]

I'm not surprised that Vcc and Gnd are simply implied.  That's pretty common practice.  The circuit itself is demonstrating how to create an oscillator and details like Vcc and Gnd are not that important.  A glance at the datasheet will disclose the requirement.

Once you have seen it a few times, it's no big deal.

No doubt. The problem is what happens *before* you've "seen it a few times".    

[amyk]

I'm not surprised that Vcc and Gnd are simply implied.  That's pretty common practice.  The circuit itself is demonstrating how to create an oscillator and details like Vcc and Gnd are not that important.  A glance at the datasheet will disclose the requirement.

Once you have seen it a few times, it's no big deal.

Also, drawing power nets would quickly make any digital schematic very confusing, since they literally go to every IC.

[T3sl4co1l]

It is necessary to specify power pins in real designs (as opposed to mere representations of them).  This even can be a bit cryptic, and prone to tripping people up.

Most EDA packages have a dialog where you can specify hidden pins tying to named nets.  This doesn't show on the schematic and you need to remember to look at it, when you have a question about where it's connected.

It's still usually a no-brainer, but there can be times when it's an important question -- and one that can easily be gotten very wrong.

Consider a circuit using CD4000 logic at 12V for analog interface, that has a digital core at 3.3 or 5V, using 74HC or the like (and maybe an MCU and some other interface junk).  You don't want to accidentally run one of the CD4000s at 5V -- its output level won't be logic compatible, and its inputs will draw power via ESD diodes; and you definitely don't want to wire a 74HC to 12V, it'll explode!

So it is a good idea to have some pins visible on the schematic, or if not, then if you are reading the EDA files, to be mindful to check the hidden connections.



Personally, I like the look of hidden pins, but also like showing power pins to the gates.  So I take the extra time to hide pins on parts that aren't using them, which requires me to go into the dialog and hide the pins and connect them to the proper nets (even though the one part with the pins visible, is already connected; some EDA packages do this differently, and automatically connect all the parts to the same net, which is a lot less hassle).

I mostly do analog and mixed signal, so it's important to know where the pins are; as mentioned above, a purely digital circuit is only going to have one supply anyway, so noting the power pins every time would probably add a lot more clutter than is worth.

Tim

[fourfathom]

And don't forget the power bypass capacitors!  They aren't shown on this type of schematic, but will be necessary if you want to actually build it.

[T3sl4co1l]

Indeed!

I tend to throw bypass caps in a pile in the corner of a schematic, and use them freely during layout (adding or removing some as needed).

Others like to associate them with respective chips.  In that case, the chips will probably be drawn with power pins, with the respective cap hanging off the same pin.  If you don't like gates with power pins, you can also make a final power "gate" and stick that off to the side (I think Eagle libraries use this by default? seems like I see it a lot in those schematics).

If doing professional work, you should be fluent in both styles.

For example I've used the first style, with customers accustomed to the second style, and took a few extra minutes to explain during review.  Namely, noting where I'd put bypass caps, that the supplies were adequately bypassed, every chip has a cap nearby, just not necessarily the ones they had intended / were expecting (by locality on the schematic).

I tend to take it for granted that I do signal quality on the fly, and place capacitors on an as-needed basis; for maximum consistency I should update schematics to reflect placement (which was missing in the above example).  Technically, it doesn't matter (the schematic is just a netlist, really), but there is extra meaning implied by schematic placement, and those meanings should match.

Tim

[Brumby]

I'm not surprised that Vcc and Gnd are simply implied.  That's pretty common practice.  The circuit itself is demonstrating how to create an oscillator and details like Vcc and Gnd are not that important.  A glance at the datasheet will disclose the requirement.

Once you have seen it a few times, it's no big deal.

No doubt. The problem is what happens *before* you've "seen it a few times".    

You get confused until:
 - You look up a datasheet for the IC (when one is mentioned) and then follow your nose through it reading the text, examining diagrams and looking for things like power connections.  Hopefully it makes sense.
 - Over time you become familiar with general conventions and then one day the penny drops.
 - You come the the EEVblog and ask!

[TimFox]

Indeed!

I tend to throw bypass caps in a pile in the corner of a schematic, and use them freely during layout (adding or removing some as needed).

Others like to associate them with respective chips.  In that case, the chips will probably be drawn with power pins, with the respective cap hanging off the same pin.  If you don't like gates with power pins, you can also make a final power "gate" and stick that off to the side (I think Eagle libraries use this by default? seems like I see it a lot in those schematics).

If doing professional work, you should be fluent in both styles.



For example I've used the first style, with customers accustomed to the second style, and took a few extra minutes to explain during review.  Namely, noting where I'd put bypass caps, that the supplies were adequately bypassed, every chip has a cap nearby, just not necessarily the ones they had intended / were expecting (by locality on the schematic).

I tend to take it for granted that I do signal quality on the fly, and place capacitors on an as-needed basis; for maximum consistency I should update schematics to reflect placement (which was missing in the above example).  Technically, it doesn't matter (the schematic is just a netlist, really), but there is extra meaning implied by schematic placement, and those meanings should match.

Tim

I once had a student technician in our lab (in grad school) who took the pile of bypass capacitors in the lower left-hand corner of the drawing literally and simplified the system by substituting one large capacitor in the lower left-hand corner of the Vectorboard.

[rstofer]

Extend to issue to FPGAs with 20 or more Vcc (and probably multiple levels) and ground.  You will almost always see the power connections and the associated bypass capacitors (lots of them) drawn somewhere else on the schematic.

See page 7 of 12 for power distribution:
https://reference.digilentinc.com/_media/arty:arty_sch.pdf

Note the number of different voltages!  Further, note the capacitor values 47nF, 470nF, 4.7uF in decade sequence.  Dave did a video on decoupling capacitors and how different values are more appropriate for different frequency ranges.  Here we see it in practice.

If I counted right, there are 46 power pins and 46 ground pins.

Most, if not all, of the devices, other than the FPGA itself, do have power and ground shown.  But it's at the package level because we really aren't dealing with discrete logic.

[T3sl4co1l]

Although that's a minor topic in itself, which Dave handled erroneously.  (Short of it is, stacking can make things better or worse, and doing it by rule rather than through understanding, is more likely to make things worse in my opinion.)

More topically; when I do multilayer boards, I tend to use very few bypass caps.  They're all working together via internal planes, so it really doesn't matter where they are, or how many, as long as the total is adequate.

Tim