RC Filter + opamp

[slashguitar]

Hi,

I'm trying to prototype something similar to Bob Parkers ESR meter with an FPGA, but instead of charging a capacitor with a constant current I am filtering a PWM before applying it to a comparator. The problem is I have 100mV at the inverting input of U2B when PWM is 0.  Any ideas what is causing it and how to fix it?

Thanks


EDIT: Inverting input....sorry for the mistake

[sub]

It looks like input offset is your problem---the datasheet lists 12mV max, which would give a 240mV output in your case.  Perhaps either try a different op-amp or build a composite amplifier.

[slashguitar]

I'm talking about the opamp on the right(the comparator). Doesn't the input offset appear at the output?(....ex....input is 0 output is 12mV).
I have 100 mV on the noninverting input

[IvoS]

If the offset is 12mV with gain of 20 coming from U2A would give 240mV or thereabouts to your noninverting pin of U2B ?? Am I missing something? 

[slashguitar]

Sorry, I ment INVERTING input of U2B (VHDL is getting on my nerve
That's why it doesn't make sense to me. 

p.s. I just measured the noninverting input and its about 20mV (1mv offset is well within spec).

[sub]

Do you mean the PWM is set to zero, or that there is 0V on the PWM output?  If you have done something like this

Code: [Select]

assign pwm_out = (counter <= pwm_value0) ? 1'b1 : 1'b0;
then you will get a voltage 3.3*2^(-N), where the N is the number of bits of resolution that you have.  I realise that this is a rather obvious suggestion.  A 3V3 IO would give about 100mV if you had a five-bit PWM.