That's a horrible circuit! At low voltages...
Start at the emitter and assume the transistor is saturated such that Vce = 0.2V so the emitter is 2.8V. The base needs to get to 0.6V above the emitter to saturate the transistor which is 3.4V or 0.4V above the 3V rail. Not going to happen.
Just 2 items to consider: What is the voltage drop across the transistor, best case, and what is the base emitter voltage.
Another way to look at it: If the emitter voltage is going to be 3.0 - 0.2V or 2.8V, the base has to be 3.4V.
The way this gate is usually used is with a much higher Vcc than the assumed logic levels. If Vcc was 12V then it isn't necessary to get the transistors into saturation to have a logic level of, say, 10V. When you deal with low voltages, the base emitter voltage and the collector emitter voltage become a significant percentage of Vcc