I want to read a 16 bit value over an 8 bit bus, so I'm using 2x 374 latches, and alternating which one has output enabled.
If I select from only a clock signal + the same clock signal but inverted through a not gate, there will be a short interval, about one propagation delay long, where both latches are driving the bus.
Is there any risk that having both latches drive the bus simultaneously could fry something? Do I have to make sure only one output is enabled at any time?
(It works in the simulator but I haven't wired it up yet because I'm going to have to order a PCB because the circuit grew large. I think the simulator I use, Logisim, mostly ignores analog details of circuits. I can't wrap my head around the different Spices unfortunately)