No one expects a poor step response at such low frequencies (100Hz).
Why not admit its a cost saving measure?
Poor lower frequency settling time is now a more difficult problem in the sense that it less understood now than in the past. I expect it in modern designs, but not old ones. Those old discrete transistor designs used lots of circuit tricks to achieve it, which are now lost.
Operational amplifier settling time is a good example. In the short term, it only depends on slew rate and bandwidth, and the math is straightforward, however over a longer period of time, it depends on thermal or electrostatic effects, which is why if you want fast precision settling time, factors other than slew rate and bandwidth are important. In datasheets you just have to rely on the 0.1% and 0.01% settling time specifications, and notice that they have very little to do with slew rate and bandwidth.
I keep laughing at the newer 12-bit DSOs, because they never settle to 12-bits, and do not present 12-bit noise performance. Such performance might be possible, maybe, but requires at least a heroic effort involving hybrid construction and lots of discrete parts.