Binary counter troubles

[MechEng87]

Hello everyone, I am new here and love the forum and the eev blog YouTube channels. I am working on a project for a counter that has me troubled. I am using g a 74ls163 binary counter and I am trying to get it to stop could time g at 9 and reset. I have done some looking online e and tried everything I can think of to get it to reset after 9 instead of counting all the way up to 15 then going g back to 0. I hope this isn't too basic a query but if anyone can help I'd appreciate it. I am working on building a light gate timer for velocity measurements.

[ataradov]

9 is 0b1001 (8421), so your stop signal is: (1 & 8 ) & ~(2 | 4). You can obviously rewrite this into whatever logic gates you have at hand. In this case you need 2 AND gates and one NOR gate.

[MechEng87]

Ok, that's kind of were I was headed but so far nothing is working the way I expect. I tried putting a diode and gate with Qa and  Qd as the inputs that would reset the timer on the next clock cycle but no luck. Is a diode AND gate appropriate? I'm using all 5 volt logic levels.

[ataradov]

You can make AND gate out of diodes, but AND gate alone is not enough here. And it is obviously better to use real gates for a real project.

[KerryW]

Actually, if you just NAND Q0 & Q3, you would get a Reset pulse at 9, 11, 13 and 15, but since it would reset to 0 at a count of 9 it wouldn't matter.

[ataradov]

Actually, if you just NAND Q0 & Q3

Good point. In that case diode AND should work just fine.

[danadak]

Do you have a race condition or not meeting PW for the reset signal ?

A scope can help here, and look at datasheet to create a timing diagram to
see if you are not meeting chip timing.


Regards, Dana.

[MechEng87]

Got it! Thanks for everyone's help, I used an AND gate on q0 and Qd then fed it through an inverter and it works perfectly. I will just use a NAND gate as KerryW suggested. Thanks again everyone. I will post pics of it when I get the rest of the circuit going