The PDN is dominated by different parts of the PCB at different frequency ranges. This includes the bulk capacitors, decoupling capacitors, PCB plane capacitance, parasitic inductance and capacitance on the PCB, capacitors inside the IC packages (if they exist) that are closest to the die and thus effective at the highest frequency ranges.
The combination of all these gives us a curve that could look something like the attached image.
From what I know, we would like a flattened PDN profile. This means that the peaks must not be very sharp. There is also the concept of target impedance that I am trying to understand. The question here is, what problem do sharp peaks in impedance profile create? Why is this a problem at all that we need to flatten the profile? This could be done by adding some resistance possibly via controlled ESR capacitors but I am not sure about other methods.