Perhaps an example signal illustrates the difference best.
Let
H denote a high sample, and
L a low sample, for a single clock cycle.
A PWM of period 37 and duty cycle of 32.4% (12 out of 37) is
H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L L L L Lbut a pulse density modulated signal with the same clock rate and duty cycle would be
L L H L L H L L H L L H L L H L L H L L H L L H L L H L L H L L H L L H LEssentially, in the same number of clock cycles, at the same duty cycle, you have the same number of high (H) and low (L) samples. Within a single PWM period, they are separated, but in PDM, evenly distributed.
While PWM has a clearly distinguished period – above, 37 clock cycles –, pulse density modulation does not have a clearly defined period at all.
Because PDM does not have a clearly distinguishable period, with quantization noise at the high end of the spectrum, it is much easier to filter: just a low-pass filter at some fraction of the clock rate. Compare to PWM, where any duty cycle except 0% and 100% have a characteristic frequency, at relatively low frequencies (compared to the clock rate used), and is much more difficult to filter out. (Coil and capacitor whine are common results from pulse width modulation, at that characteristic frequency.)
Personally, I like most the fact that pulse density modulation can be adjusted at any clock cycle without any extra work; unlike pulse width modulation, which can only be modified effectively once per each period.
You'll usually see PDM defined as a function which converts an analog sample (or discretized analog sample), once per clock cycle, to a digital signal (high or low). That is useful for signal analysis and mathematical treatment, but it isn't useful for hobbyists like myself that would just like to
see what such signals look like.
Therefore, let me show you a pseudo-code approach to generating PWM or PDM signals – much like the one I showed you above, but something you can experiment with.
Since PWM operates in full periods, we'll let
N be the number of clock cycles per PWM period. (We will use it for the PDM as well, to make the two pulse trains easily compared/comparable.)
Let duty cycle be
D, between 0 and
N, inclusive. (So fractional duty cycle is really 100%·
D/
N.)
To generate the PWM signal for one period:
For T = 0 to N-1, inclusive: If D < T, then: Output level is High Else: Output level is Low End If End ForTo generate the corresponding PDM signal:
V = 0 For T = 0 to N-1, inclusive: V = V + D If V ≥ N, then: Output level is High V = V - N (or, equivalently,
V = V modulo N)
Else: Output level is Low End If End ForI guess I could create a web page (similar to my
FIR Filter Analysis web page) that would let one play with these visually, but I feel a bit too lazy today; apologies!
For the PDM (latter) case, note that
N is completely arbitrary, and only defines the range for the duty value
D; and that
D can be safely changed to any value between 0 and
N, inclusive, every clock cycle. On the other hand, PDM generation does require an addition on every clock cycle, whereas PWM is much easier to generate (digitally, just a comparison).