@ smokey , well i am still learning. thanks for everyones tips n nice technical threads that i can learn from. n of cos EEVblog for putting up with my immense nonsense
and splatters of rather noisy pic / plots.
@ retrolefty, i cannot be classified as voltnut (and i have no qualification to be 1 anyway), the best VREF i have outside of a DMM is a voltagestandard from doug (not that it isnt good enough). i think voltnutters may need a diff certification standard to certify voltnut-ness, maybe to DIY a VREF of verifiable 1ppm nut-ness
. and to top it off, this K2015 is uncalibrated, i do not have the ability to define a volt accurately beyond 10mV (in my own opinion).
@ dr.diesel, i read in keithley pdf, azero on will make MCU measure VREF n zero when it is sampling input. i read that some suggests to improve sampling, instead of azero always on, they program it to cycle on/off once every minute. im not sure if newer keithley gear does it in per sample basis, the pdf seem to indicate the K2015/2000 does it on per reading/sample (i cant remember which pdf it was).
and to continue with some "fault" finding, i re-measured the floating "noise". (for ref, VR 115 and VR116 is swap around on my PCB, with pin 1 VR115 connected to source, not VR116 p2 to source). trace is for pin1 VR115 (which is tied to opamp input), vert is 250mV/div, horiz is 2ms.div (i beliv i made a mistake "zeroing" my scope previously and got the units all wrong lol). the huge signal is with uni-t plugged into inputs, however, w/o anything plugged in, the noise is very low pic-161054 (vert 50mv/div). shorting plug, noise is undecipherable on scope. i think the jagged noise has something to do with my neighbor's new air-conditioner installed today
my theory of this noise, is it could be the higher input impedance of new opamps. i derive this hint from trying to measure a 9v battery, after removing the input, the voltage take 10seconds to reach 1.5v, and is still trying to dissipate. hmmmm ... with the DMM powered off, pin 1 VR115 actually only have 116ohms to AGND (input low). i wonder, did the JFET have a switched sampling and forgot to on its discharge? or it doesnt work that way ?
next i try something, i tie a 1M R across U107 to AGND. this results in the next reduced trace pic-163734 (250mV/div).by doing this, it also destroys the DC accuracy
.
next trace of +15 rail regulated noise, which i suspect the VREG did not fully regulate the input raw. causing the peak section to bypass more noise.
i think i should try to solve the DC rail first. maybe a PMOS/NMOS low drop stage instead of a LM29xx.
so... it seems i did not really solve the noise at all from that last AGND tie up *sigh*, i must have miss-read the noise with the input open.
as consolation to myself, i add this gif chart. some logs before i stop logging to do the above rummaging in the innards. note the log in bottom half with azero off, esp
1NPLCx50repeating-average. it seems it is quite capable of maintaining a very consistent /predictable error rate, which seems like a good thing in long term logging? yes? esp note logs which exhibit low KURT/SKEW = a flat-ish plot