my noob journey to lower DMM noise (keithley mods)

[3roomlab]

according to the service manual, when 1000v/100v range is engaged, the solid state protection segment is "OFF". what i dont understand is i do not see a active power turning on/off the 2 MOSFET. can someone enlighten me how does using 3 opto-isolator switches those 2 devices on or off?
after seeing this http://www.discovercircuits.com/H-Corner/bidirectional%20solid%20state%20relay.htm, i am starting to understand, but the optos get induced voltage?

in the previous short circuit fault, where U114 was fried, it may have caused some inconvenience to U107, if U107 is damaged, will it cause -ve voltage to creep into "HI" input rail? the previous fault observation was that  likely U114 pin5 became shorted to -15, this caused VR105 to go hot (in actual circuit VR105 polarity is reversed)

i think the extra fault is lurking somewhere here, where some -ve voltage leaks into "HI" input rail

*edit plot insert (all are 1NPLC AZERO=on, no REL/math/AVE)
@1kV, STDEV = 110.41uV, p-p = 688uV (plot 0005)
@100v, STDEV = 36.6uV, p-p = 254uV (plot 0050)
@10v, STDEV = 1.093uV, p-p = 6.3uV

yep there is def something else i need to shoot, as the range shifts from 100/1000v to 10/1/0.1v. the average swings from +ve to -ve . more JFET perhaps
idea for next mod, maybe i should just really stick the TO220 VREGs to the metal chasis via some solid insulated heat spreader ! MICA film ?!?

[Kleinstein]

Open circuit readings are mainly due to bias and leakage currents. So after lots of soldering leakage currents can add up. Also changing the FETs and OPs can increase the bias. Keithly used the rather high noise LTC1050 because of the low bias - though stragely for bootstrapping they used the AD822 that may have quite some bias.
You can measure the current by having a large resistor (e.g. 1 M) acoss the inputs. Usually this should be less than 20 - 100 pA (depends on DMM model).

The LTC2057 is much lower noise than the LTC1050, so no supprise to see less noise. Now the following stage and the adc itself might be higher noise.  The down side is the possible high bias current and thus some offset.

2 of the 3 Optocouplers at the input protection are not normal ones, but photovoltaic types: they have large Photdioes (several in series) at the reciever side and worke like a weak, low noise isolated floating power supply.  The two mosfets are there to short out the protection resistors when the volateg signal is inside the valid range. This is done to reduce noise.

 If turning off the FETs does not work some parts may get fried in case of high overvoltage (e.g more than 100 V) at the input. So before testing with higher voltage you should check this part: at least looking one the sending side of the optocoupler and measure the voltage of the floating supply. Also check the FETs for conduction (might got damaged by ESD).

[3roomlab]

mmm i have to dig deeper, maybe desolder and check each opto unit 
with my UNI-T jammed into the input jack, the handheld register about 140mV voltage in the low range (feel like too high to me), and something else in the 100v/1kV range cant rem what it was. the JFET in the switching array is all swapped except for ohm source, i cant find the J270, i am suspecting this JFET as well, but im not sure. on the PCB there are about 4 kinds of switching JFET, but in schematic is only 1 type. i wonder, did previous owner repair it? haha !

on the tip of A/D side noise, there is a A/D gain stage using AD711, it sports an active offset nulling, would it be risky to replace it with a autozero opamp? i am thinking AD

if the optos are fried, im in deep shit as E14/RS here do not have those variant. except mouser/digikey. i hope i do not have to buy from them . the shipping is killer  . there is no indication in svc manual what voltage to expect from opto, so i think i just have to "grope" further to see how the opto turn it on. (btw do you know what could be a possible equivalent?)

for all the work and experiment, here is the summary of todays short tests (vs tests of old 10NPLC). 1NPLC nearly matches every 10NPLC done before. best part is yet to come, 10NPLC numbers and i think i will try NPLC 100 with more confident as the low noise now is really low noise !

(note that tests 1000/100/10 are using results of DMM standing upright on sides, 1v/0.1 are sitting flat. the side posture seem to be better)

[Kleinstein]

The AD Gain stage is a rather tricky combination of 2 OPs. The lowe frequency part should mainly depend on the OP177, not the AD711. The noise from the OPA177 might still be lower that the LTC2050, at least at not so low frequenies. So I don't see a lot of room for large improvements there.

The whole setup is not made for very low noise - a really low noise unit would use the initial amplifier for at least some gain as well. But this would essentially mean a complete new design.

The next step would be checking for the input protection to work and check the bias current. I don't think more noise data are needed now. This bigger Problem is likely Bias current. 140 mV at presumably 10 M input resistance of the UNI-T meter would be something like 14 nA of leakage - this is way ( at least a 100 times) to much. Looks like a broken JFET or lots of flux / dirt. The better test would be just a 10 M resistor at the input.

The switching JFETs might have to be selected / tested low leakage ones. Also make sure to have the case closed, as thin SMD parts may react to light. No low leakage in bright light.

I won't exect the optocouplers to be fried - like LEDs they usually last quite long. The dataseet of the OK should give a voltage value and also the FETs have a voltage they like to have to turn on. Even then to little voltage to turn the MOSFETs on, would result in more noise, but not in a failing protection. The protection might fail if the thrid OK is not working but this should be a nore normal one. Also it should be possible to test this circuit rather well in circuit, by just looking at the voltages ( e.g. gate voltages of the MOSFETs, when changing the input voltage ( e.g 1 V range and test at 0 and +-20 V at the input).

P.s. just looked at schemattics: the K2000 uses one special photovoltaic OK and two more normal darlington ones. However this part looks rather strange so the K2015 might be different there !.

[3roomlab]

ah the entire PCB is IPA-ed and ovened dried (lost count, by now maybe washed 10th round). so i know for sure PCB wise it is flux-free. ahhhh the smell of concentrated alcohol when the oven door opens, maybe it is 1 month worth of beer there  *hic*

i think i try JFET hunting. but i have no more spare mmbf4393. the other 2 suspicious candidate are a lm339 n DG211.
on the side note, i did measure a few JFET with high resistance when 4393 are suppose to be "open-ish" 100ohm? that would be a sure fire way to say it is a problem JFET wouldnt it?
also i am considering to try MMBF4416A, it look like a close match, with higher voltage rating?

[Kleinstein]

The 4416 seem to be only 30 V (gate source) rated, this may be to little. So I don't think they are a valid replacemant, as they are used up to 30 V and possibly silghtly more. So they should be really specified to 40 V at least. With the gate open the resistance is not well defined. To get a usefull reading, have it connected to source or drain. Than something like 100 Ohms is correct.

For the LM339s it should be possible to measure the voltages at there outputs, if they are OK. It's usually a go - no go part. I would not expect a partially working one.

I see no DG211 in the input part, that could cause extra leakage, and I won't expect to have one there. 

One could do a few more measurements to check which of the FETs may be the bad ones. Interesting values would be the DC readings (0.1 V range and 100 V range) with 10 M between the inputs.

And the for an inital test one might get away with some, like the ones to turn on for ohms to be not populated.

It is also possible to have damaged a capacitor by excessive heat. 

[3roomlab]

ok, now i see why even the mmbf4393 also spoil easily
https://www.fairchildsemi.com/datasheets/MM/MMBF4392.pdf
they are also 30v

i should say 4416A, they seem to be 35v

U103 = DG211, it switches front end stuff

100mV 10NPLC rough test, looks like a low p-p

**edit i went to search in mouser
how about BSR58 / mmbf4117. -40v

[3roomlab]

Mr popcorn noise is back. even being heavily messed about by pops and dips. this 100mV plot managed to hit STDEV of 58.95nV, p-p noise is just 430nV. the plot is 1NPLCx10REP, 2400 samples. the tolerance width is now so small, any small amount of pipsqueek noise will send the plot into a rollercoaster ! 

update to show 3 plots, NPLC1x10REP, 0.7sec/sample, 3600samples
plot 1253, skew: -0.409, kurt:1.458, STDEV:72.46nV, p-p:611nV
plot 1153, skew: 0.016, kurt:0.084, STDEV:64.76nV, p-p:453nV
plot 1111, skew:-0.111.kurt:0-0.086, STDEV:66.97nV, p-p:436nV
all plots with fan, and now to try w/o fan.

looks like i will need to grab 1 of those $20 LCR to measure the JFET (n a short readup on JFET http://www.diystompboxes.com/smfforum/index.php?topic=100990.0)

update plot, circular fan removed
plot 1429, skew: -0.011, kurt:-0.032, STDEV:51.24nV, p-p:375nV
it seems even the slow fan circulator has become more of a noise problem than it should

[Kleinstein]

The MMBF4117 is rather high resistance. The 4119 would be slightly better (lower Ron). It schould be OK for some of the switches, but may not work well for all of them. E.g the two at the low end of the high voltage divider are better lower resistance type - possibly only one, for a more suitable part.

With these FETs you might have to check the specific manufacturer. For example the 2N4393 (TO18 Version) is rated 40 V in some cases.

U103 is in the AC part (behind the coupling capacitor) of the circuit - so no DC leakage from there. It seems to be for something like speed up of recovery from DC steps in AC mode.

If there was trouble with the input protection you might want to check the sending side of U107 (one of the optocouplers). This chip is also used from clampling - seems to be low leakage too.

There is really not sense in doing noise testing before the bias problem is fixed: you may have to change the LTC2057 worst case, this one possble source of the high bias. The other point to check is offset in the 100 V range.

[3roomlab]

i think NXP's is the next equiv http://www.nxp.com/documents/data_sheet/PMBFJ111_112_113.pdf
the 4119s to order is in 1000s reel, the NXPs to order is eta 2016 end of jan 
i think this is all that is left with 40Vbr, https://www.fairchildsemi.com/datasheets/2N/2N5460.pdf  --> 5462
ah P channel, wrong item ops
searching 1 tier lower, Vbr 35v, i get mmbf-J112/J111 from fairchild <--- i think i could either try this or wait for NXP
but best search result is the vishay, in the form of LM399 !!! 

yea i know, logging anything in this state is pointless, but there is nothing else to do with the DMM atm. but i dont mind saving some "broken" data just to know it

i made some more measurement of the floating voltage
DCV 100mV, DMM = 3mV DC, uni-T = 140-150mV AC
DCV 1V, DMM = 4mV DC, uni-T = 135-145mV AC
DCV 10V, DMM = 4mV DC, uni-T = 135-145mV AC
DCV 100V, DMM = 2.5mV DC, uni-T = ~110mV AC
DCV 1000V, DMM = 2mV DC, uni-T = ~110mV AC
ACV 100mV, DMM = 23mV AC, uni-T = ~21mV AC
ACV 1V, DMM = 22mV AC, uni-T = ~20mV AC
ACV 10V, DMM = 27mV AC, uni-T = ~23mV AC
ACV 100V, DMM = 77mV AC, uni-T = ~21mV AC
ACV 1000V, DMM = 0.71V AC, uni-T = ~21mV AC
the pic is a screen grab off a low end dso, it is also the waveform i remember seeing going around the Q101/102. now that i recall these, i think it might be leakage from ohm source.

it seems net144/net140, which goes thru U107 to net145, could be the source of the leak, if gate leakages are the source.

[Kleinstein]

The open measurements are pointless. To get a bias current reading, connect something like 10 M or 1 M between the inputs. Also the Uni-T meter might do it, if we know the input resistance. But this would mean using the DC mode. Also the polarity might be important.

Normally the voltage at U107 (sending side) should be close to zero ( < 5 mV), and U107 should not give significant leakage. I won't expect high leakage from this path unless U114 is broken.

One test to check the OPs for bootstrapping would be using the 10 V and 100V DC range, have something like 3 V at the input and measure a few voltages inside.

[Macbeth]

Very interesting thread. There is one thing I've noticed with K2000 vs K2015 and that is the K2015 appears to be more noisy (when shorting the inputs). I'm not the only one to have observed this, and my first conclusion is this is due to the DSP board along with its own mains transformer sitting right next to the input terminals. Of course this noise is still within specification, just not as good as the 2000.

I've also wondered if this is why Keithley unhelpfully disabled the BUILT-IN self check on the 2015, despite when looking at a hex dump of its firmware the code is all there!

One thing I did was swap the K2000 A06 firmware with my K2015 firmware just so I could run the built-in tests. This required a back up of the calibration EEPROMs of course. Interestingly the K2015 failed the first two tests 100.1, 100.2, but all subsequent tests passed.

I disconnected the THD board and ran the tests again and they passed completely! However, when I came back to it they kept failing again. I wonder if disconnecting the transformer would fix that? I was more concerned with all the other tests passing at the time anyway so didn't give it much further experimentation...

[Kleinstein]

Noise at the gate of Q1 is not a problem. This MOSFET should be on when a normal measurement ( not 100 v or 1000 V) is done - the question is more the DC level, not the small noise.
The power for this part comes through the optocoupler from the 5 V supply - so noise is expected though filtered. It may be possible to do some more filtering here, but I doubt is will change much. I have not checked, but to get low noise the 5 V used here and for the input relays should not be the noisy digital supply. So a look at the 5 V (e.g. relais) might be a good idea.

More interesting testpoints would be pin 2 of U107 (optocoupler) or pin 7 of U114 (protecting ring at input) and pin 1 of U114 (protecting ring and supply of LTC1050). Also the output of the LTC1050 would be a good test point.

[3roomlab]

i think i solved it. it is the AGND. the ex AD822/OPA2140 cluster i thought did not need a AGND shortening before as it was only a guard/zero-buffer-floating, now due to the increased sensitivity, a AGND shorting to the rest of the clusters' AGND removed the noise !
(during the course i took a few more scope pics, including irrelevant noise of the 5000lm flourescent light, LED light, USB charge, etc. the equipment with the "pretty noise imprint is the nidec fan supply line. http://3roomlab.blogspot.sg/2015/12/looking-for-trouble.html)

now its quite clean !


on to log some more serious DMM noise !!! to verify the fix

edit : updated blog with caption notes

[Vgkid]

Lets see those results.

[3roomlab]

NPLC10 warm up run, looking normal. no more squiggly dips n pops.
this skewed plot have a STDEV of 62.11nV, and p-p noise of 411nV
now that sensitivity is increased, maybe the entire AGND mod need to be expanded. maybe the opamp section need a tinfoil "hat". because waving my hands does change the guard output !

[Macbeth]

The Tinfoil Hat goes without saying. But I think you have to get in touch with Monster cables for the interconnects at a minimum. But really I think they are cheap shit for low end fools. You should get some Nordost Odin, which is apparently 99.999999% oxygen free. 

(Oh but a little more seriously, have you tried disconnecting the THD board and the transformer next to the input terminals? - surely Keithley know better, but why did they disable the BUILT-IN self test on the K2015? My own datapoint would suggest the extra THD board adds a bit of noise, but it's nothing more than conjecture at this point!)

[3roomlab]

The Tinfoil Hat goes without saying. But I think you have to get in touch with Monster cables for the interconnects at a minimum. But really I think they are cheap shit for low end fools. You should get some Nordost Odin, which is apparently 99.999999% oxygen free. 

(Oh but a little more seriously, have you tried disconnecting the THD board and the transformer next to the input terminals? - surely Keithley know better, but why did they disable the BUILT-IN self test on the K2015? My own datapoint would suggest the extra THD board adds a bit of noise, but it's nothing more than conjecture at this point!)

im not sure if i have the budget to grab special materials like nordost odin, i am only reaching for what is convenient/feasible i atm. i have the idea to wire out a terminal block, instead of using the build in banana sockets, with that, it could be possible to chieve good results even without using premium copper 

yes i did disconnect the DSP this round to see if it does have a noise impact, but i will only know later with more logs. the pic attached is now what the current mod look like

*EDIT thanks to kleinstein for continually giving me tips for improvement n repair

[Kleinstein]

Some shielding might help a little - though the main advantage would be likely in the very fast ( less than 1 PLC) modes, as a main funktion is to remove coupling to 50/100 Hz. Also HF coupling (e.g. from the DSP) may be reduced, but the influence of a shield that is not 100% closed on HF is hard to tell  it tends to concentrate HF towards the edges, so a shield may make things worse at some places.

Whith changes in the AGND part, you have to be carefull, not to introduce errors or offsets. Usually Keithly do get the GND layout correct - adding extra connections may introduce loops and errors due to stray currents in some ranges. So even if the DCV ranges might get sightly better ohms or amps readings might suffer. So I would only add things after knowing exactly where in the circuit the extra connection is. For HF "noise" I would also measure  first and solder only than.

There still seems to be quite some offset - keep that in mind too. Input bias currents or offsets are also important parameters for meter qualitiy.

[3roomlab]

@ macbeth, the moment you've been waiting for. guess which plot has DSP unplugged or which is the plot with DSP plugged/powered.

plot 0705 STDEV 142nV, p-p 1000nV
plot 1221 STDEV 145nV, p-p 1016nV
plot 1351 STDEV 145nV, p-p 977nV

[3roomlab]

i went ahead to do the "tin foil hat". i use some disposable aluminium kitchen baking tray to cut the "hats" n some kapton tape to insulate. 2 areas to experiment with, the GPIB digital section, the analog section with the sensitive opamps (top and bottom). to understand what noise is there

this is the example of the noise from VFD ribbon cable, just by pointing scope probe at it
http://1.bp.blogspot.com/-iei842h_OnY/VnHmQCkzEuI/AAAAAAAACgA/DLa8d7zdGL0/s1600/20151217_055434VFDribbon.jpg
this is noise from U156
http://2.bp.blogspot.com/-vBNnQMlIjQU/VnHmTNGe8XI/AAAAAAAACgY/gHw3d2ZMfmQ/s1600/20151217_055558u156.jpg
scope parameter is 1mV/div, 1ms/div

i remember reading/seeing somewhere that sticking a metal foil on top of noisy IC help to absorb its EMI in the immediate "vicinity", i cant remember where to find this information anymore, i wonder if anyone know if this is true.

with the "hats" in place. here comes the logs.
the funny thing that happens now is that, there doesnt seem to be noticeable improvement, until i turn the unit on its side. so on top of being a EMI shield, it is also creating a separate thermal cavity which is helping the stability in some way. and due to the marked noise spikes, the p-p noise reaches 1152nV ! bah ! otherwise, the interesting setup gives a STDEV of 134nV (still way more noise than 1NPLC 54nV of keithley 7510 ! i wonder how much noise does 3458a has?). but by far, the improvement are also not by leaps and bounds without "hats". the majority of the noise is still the noisy circuits.
on second look, it doesnt seem like a very marked improvement, or maybe it needs a few more hours to settle ... ... ...

at a glance, it seem possible to lower even more noise (without the few spikes, the p-p noise seem to be around 750nV) if the tin hats can be painstakenly cut to "hug" the PCB on both sides, and set in place maybe with superglue? so in that way, 1 could then make a mini "great wall of china" around what needs to be "walled up". maybe? maybe not? 

  i need to destroy more noise !

[Kleinstein]

The shield has mainly 4 effects:
1) line related capacitive coupling is reduces. This might be noticeable at less than 1 PLC readings, but likely not at 1 PLC and slower.
2) It will influence HF (e.g. 10 MHz range) "noise". However as the shield is not really closed in the HF sense, it is not clear if things get better of not. It temds to make things better, but not necessarily.
3) It changes the thermal design and keep turbulent air flow away from the circuit. This can reduce LF noise, as thermal EMF and local themperature variations are one nosie source in the sub µV arange. On the down side some part may get hotter as airflow from the fan may not reach the parts.
4) it makes capacitive coupling (especially in the ADC section) independent of external cable movements. But instead movements of the shield could have an influence.

Before more shielding is tested, don't forget the bias / leakage current. This is the first thing to be fixed. The changed OPs are a real improvement only if bias currents are stay small.

When lloking for noise reduction, it's a good idea to identify the soures, both from the theoretical side (schematics / caclulation) and measurements at different positions (e.g. compare noise in DCV and DCA modes and do the math). This really helps to find the weak spots and parts that can't be improved (e.g. resistors that need to be there). With the OP changed I don't know which is the main noise source now.  Nobody cares about repeated noise measurement with just a shield more or less. The interesting part would be using the same setup and get data 0.1 V / 1 V / 10 V / 100 V and 10 A (or 1 A)  range with the same NPLC setting (e.g. NPLC=10 ) - no need for really long datasets, just 200-500 readings without much drift are enough, especially if the same lenght is used for all sets.

The setup of the K2000 is not optimized for low noise (using AZ OP instead of low noise JFETs, separate buffer instead of amplification in first stage). So you can't expect really low noise like from the high end DMMs. Noise data for many DMMs are in the separate thread on DMM noise.

[Macbeth]

@ macbeth, the moment you've been waiting for. guess which plot has DSP unplugged or which is the plot with DSP plugged/powered.

plot 0705 STDEV 142nV, p-p 1000nV
plot 1221 STDEV 145nV, p-p 1016nV
plot 1351 STDEV 145nV, p-p 977nV

I would guess the middle one, because it showed a barely noticeable but worse change, so you connected it back for the last run 

So there goes my theory 

[3roomlab]

the plot 0705 is reconnected DSP , the other 2 are w/o DSP on.

logging update:
after some hours of warm up. it does seem the "tin hat" did help squeeze down some noise. (these new plots are also with DSP connected). it also seem like 1v range more STDEV is experienced. the plots which represent "tin hat" are leftmost s/n 222-238 (bottom 1/3)
and strangely somewhere in between while i wasnt looking, the temperature dipped from 38.3 to 35.3 

*edit
(pic 2, green = 10v 1NPLC overlay on red 1v 1NPLC, 10 units of red exactly sits on 1 unit of green "stepping") i did a small experiment regarding range/NPLC resolution which i previously did not understand. in 100mV range there is enough resolution to define 0.1uV, but as the voltage range scales up, resolution scales down equally. so i have to assume, every scaling up of 1 range, the NPLC (or REP) needs to be increased by x10, in order for minute changes in 0.1uV to be readable (100nV resolution which is in spec)

conclusion
100mV - 1NPLC usable to read 0.1uV
1V      - 10NPLC must be applied to read 0.1uV
10V    - 10NPLC*10REP must be applied to read 0.1uV
100V ? -1000NPLC?
1000V? - 10,000NPLC?
however it is likely this only applies to my modified K2015, as it now sits well below normal factory noise (or so i assume). it is likely a stock K2015 will need to apply NPLC10 to 100mV to resolve 0.1uV? maybe?

[Kleinstein]

Comparing the noise in 100 mV (about 137 nV ) range and 1 V (180 nV) range, one can see that much of the noise is stil from the input part and ADC gain stage. Some noise is also from the ADC Stage, but not very much, even in the 1 V range.

The difference is due to reduced (by a factor of 10 in voltage and 100 in power) ADC noise in the 100 mV range. So in the 100 mV range noise from the ADC is still neglegible and even in the 1 V range it is still quite small: the about 180 nV in the 1 V range come from about 135 nV of the input amplifier and Gain stage plus about 80 nV from the ADC (inlcuding reference) itself.

Bandwith für 1 PLC should be 25 Hz plus an slightly uncertain part from the autozerophase. So getting date without Autozero might be useful.  So the expected noise density is about 28 nV / Sqrt(hz) if 25 Hz bandwidth is assumed.
Known noise sources als the LTC2057 and the OPA177 (U132 in the gain stage) both at about 11 nV/sqrt(Hz) and something like 15 nv/sqtz(Hz) from R304 (20 K). Some more might come from the AD711 (U166) - I still don't see how exactly the two work together.

So much of the noise is acouted for, and not much is left to HF coupling or thermal effect (at least at 1 NPC). However thermal effects are often slower, so may show up stronger at 10 NPLC. So I don't see much more room for improvements without major changes.

Interestingly R304 is seem to be a large portion of the noise, but there is not much you can do about this as the resistor is needed for protection against overvoltages. In a carefull test one could get readings with this resistor shorted - but I would not change much there for later use. Data from the current ranges could give noise from just the gain stage.