Thanks very much for the reply. Looking at the continuous option first, since an HV 595 would be right next to each digit, and the cathodes will be grounded, there shouldn't be any problem with the load lines. But the Uno would be directly driving the SPI lines, and the serial clock in particular would be fanned out to each of the 11 chips, at varying distances. I've seen schematics of button boards and such where this is done, but don't know if it actually works. Serial data would only go to the first chip, and is then refreshed going to the next chip in the cascade. But I guess if the clock line is a problem, a single-gate buffer of some kind could solve that.
That's normal, CMOS fanout is quite large. If there's a lot of distance (delay) between chips, you can end up with indeterminate or ringing clock waveforms and get inconsistent and lost data (multiple shifts per edge). This is due to the characteristic of a source-terminated transmission line, that the voltage level on the line, at a middle position, is Vstep/2 after the incident wave, until the reflected wave passes.
If everything fits on a breadboard like pictured, it's likely that delay is less than the risetime, and the clock will be well-behaved.
In the multiplex option the SPI lines would be quite short, and only going to one chip. But the load current lines would fan out over some distance. I figured out a way to avoid having to power down those lines during changes (to avoid ghosting) by triggering all the latch pins from a single GPIO pin so both the anodes and cathodes change state at the same instant. That means that if the refresh period is 100us, that's the maximum speed at which the load lines would change state. If I understand what you've said, that's not likely to cause a problem so long as the layout done properly.
You'll still get a faintly visible ghost image, actually. The load switches won't turn on/off at exactly the same time, plus the one column's capacitance has to discharge through the newly activated rows (or, even if there's a pulldown resistor to discharge it, some charge will take the LED route). Probably nothing that would be visible daytime, but indoors or dim conditions perhaps.
But yeah, nothing wrong with that at all.
As a general rule, only use what bandwidth you need. This might not be optimal, as you're starting with the risetime of the Arduino, and the driver IC(s), and so filtering would be needed -- a tedious parts cost.
Sorry, you've lost me.
Bandwidth is not just the clock rate, but the edge rate too. You might only be toggling columns at some kHz, but the MCU or driver's risetime might be a few ns, thus the bandwidth extends into the low 100s of MHz. You need a scope of at least as much bandwidth to properly resolve the risetime of such a signal, and you need a medium of such bandwidth to transport it (bandwidth, usually in terms of attenuation per distance vs. frequency, is a characteristic of a real transmission line).
Filtering components can be added to slow that down (give or take clock pin specs -- in the extreme case, a schmitt trigger might be needed to honor maximum risetime spec), and thus avoid activating any signal quality and EMI issues in the corresponding frequency bands: can't be an EMI problem if you aren't operating in that frequency range to begin with. Conversely, filtering makes your circuit more immune to interference in the cutoff range.
In multiplexing, the SPI transfer would be initiated toward the end of the timer ISR, and only needs to complete before the next interrupt. The slowest you can run SPI on the Uno is at 1/128th the speed of the 16MHz system clock, which would be 125KHz. I think the ISR will be fairly short, so that should work timing-wise. I just don't know how good the GPIOs would be in driving these lines.
I mean, they're made to do it. And a heck of a lot faster than that; GPIOs typically have a toggle rate equal to peripheral clock (which is trivial on ATMEGA, but most ARMs for example, the CPU can run much faster than the peripherals).
Average HC/LV family CMOS pins (and by association, most CMOS ASICs -- but not guaranteed, always check the datasheet!) have a source resistance of 30-70 ohms (depending on type, supply voltage, temperature, manufacturing variation, and polarity -- pull-up (PMOS) is usually weaker), typical trace/cable impedances are 40-120 ohms, so a direct connection, or with a small source termination resistor taking up the remainder (typ. 15-47 ohm), achieves a source termination condition, and good signal quality will be had at the far end of the transmission line.
Note datasheets don't spec pin resistance per se, let alone the output V(I) curve; you have to infer it from the VOH/IOH and -L parameters, which are usually given as worst-case, and the average case might be 2-3x better than that.
MCU GPIOs can be stronger; they may be made to drive LEDs or other loads directly, i.e. spec'd for 20mA output, or even more, at low voltage drop; again, check the datasheet. That's simply solved by choosing an appropriate source termination resistor.
Mind, I'm just going off the cuff here, responding to comments as they come. If this isn't making sense, you might want to raise some more pointed questions -- what is a transmission line, signal quality, etc.? Have you done reflection (ladder/lattice) diagrams before, do you understand how reflections propagate on a TL? Do you know about logic pin equivalent circuits, and how they interact with TLs?
Tim
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