I adjusted the zener place like you posted earlier. I use the 1k resistor as a discharge resistor for the gate as I saw this from other places so I trusted it. Now, for the Vds being a max of 10v... I didn't know that? so I thought that putting a 20v is the best choice because it is the maximum voltage for the gate. So if it does reach 10v as a maximum, then what is the problem? or is it dangerous to reach 10v?
I presume you mean Vgs (not Vds) , the oxide on the gate is incredibly thin, and voltages above 20v will likely cause the oxide to punch through, after that the MOSFET is useless. The section where is says V
GSMAX is titled
"ABSOLUTE MAXIMUM RATINGS" you need to ensure that your design
never exceeds any of these at
any time, under
all possible abnormal operating conditions. With most mosfets the threshold is around 3v , to get 100uA of current at 5v it is generally completely ON, at 10v it is still completly ON, but the transition from resistive to constant current has moved up a bit, after 10v no increase in performance occurs.
The threshold voltage varies between types , typically 1.5 to 2.5 for logic level (intended for 5v operation) , 3 to 4v for normal mosfets, intended to be driven with MOSFET drivers from a 10v supply, and then you have a few high voltage MOSFETS with Vgth from 1 to 15v (600v to 1000v Vds).
The image below shows the gate curves as you can see 10v is off the top of the page of fig7 , and R
DS has flatlined by 10v.
Note the V
DGR rating as well, this means if you have 30v across D - S , then you can't put more than -10v on the gate (The internal diode in the zener limits reverse voltage to 600mV)
You need to respect the V
DS rating too, for example if you connect the MOSFET through a 1k resistor to a 50 supply it will probably comfortable sit at 45v, swing to 45v in a SMPS power supply and the MOSFET will get very hot from avalanching all the time - see the avalanche rating in millijoules. Operating most MOSFETS , especially those above 400v, at 60% of the max rating will make them impervious to SEB (single event burnout), this is caused by neutrons that are passing through us all the time. At 60% of V
DSmax , the failure rate will be 1 in 1billion hours (a couple of centuries) , at 80% it is 10 times worse , at 100% it is 100times worse, so failure in a decade or less.
What is the purpose of D1 in your image? plus, is it ok to put a 0.1uF capacitor after the 1k resistor to ground?
By after, you mean below the 1k resistor?, this is basically the output, yep you can put a 100nF there (i.e. across R13), you might want to put some bulk capacitance there too (100uF electro) but be aware the ESR of this cap can affect loop stability. D1 is there to stop C1 floating off when the voltage setpoint is dropped suddenly with a capacitive load, it also helps discharge the gate capacitance of Q2, and hopefully reduces overshoot, it also means the op amp may be current limiting briefly , but that won't bother it.
Until now I couldn't get why some MOSFETs are "suitable for linear operation" and some are not. I know that low R_on is good for switching application because of low power drop or something... but why is it not good with linear assuming it handles huge amount of current?
In theory all MOSFETs have the same behaviour model , that is determined by length to width ratio of the gate , and the device area. In practice it's more complicated. FETS have two operating regimes - constant resistance or constant current , with the gate voltage determining which resistance or current. To get linear type operation in a power supply you should be operating in contant current mode, as this provides inherent rejection of ripple on the incoming supply. (In the resistance mode you basically have a resistor connecting the incoming ripple to the load). You also need to make sure the MOSFET is operating where the small signal gain doesn't vary much with load. A big problem operating with large area (low Rds) is the drastically nonlinear capacitance variation at low V
ds , this can seriously mess with closed loop gain at 10kHz and above, which is the usual trouble region for stability. The PSMN1R4 is better than expected as regards capacitance rising abrubtly at low voltages (see figure). However it does have ~ 1nF of miller capacitance (Crss) at 1v, this miller capacitance needs to be multiplied by the voltage gain across the MOSFET, (which can be quite high with a low Rds device) even with a gain of 10, you have 10nF effective capacitance, and the 22R resistor produces a pole at ~1MHz.
Maybe you could consider what I said about the continuous 1v drop across the mosfet which makes a maximum V_ds of 1v... so I guess this is good for my application. You said (or the others) something about low gate capacitance... What is the value recommended for linear regulators? The last one I mentioned (BSC900-something) has quite good one (relative to the famous IRFP250N). I ask too much because I want to understand better, not just stick to what is shown online.
The IRFP250N would , on first glance be a good choice for linear operation, low transconductance, easy to keep cool, but the gate capacitance, particularly miller capacitance is very bad at low voltages 2.4nF at 1v.(see figure)
The RFD14N05 is pretty good for linear operation, it has quite modest capacitance (see figure), but the graph doesn't go down to 1v. We normally add an external 220pF miller capacitor to get nice controlled slew rate on some comms drivers.
If you want to stay with the PSMN family , randomly picking an 11mR device PSMN011-60, this is well behaved low conductance, and low capacitance 200pF at 1v (see figure) .
What I saw from your 3 schematics is that the modern mosfet is the best somehow... the op-amp is more stable with it and the output voltage too. Correct me please if I am wrong.
Don't believe everything in sim's , but it does look better than I expected. If you want to use the same device for linear and switching, maybe a PSMN4r.... (4mR )should be reasonable compromise (that's 22Amps usable current for the SMPS). It probably works as well as it does because Q1 and Q2 together act as a follower, the effective small signal impedance at the emitter is much lower than the 1k it looks like at first glance. My circuit has fairly low loop gain so that makes it more stable.
Originally I wanted to put a ferrite-bead after the pre-regulator but I dropped the idea. Now for the gate of the mosfet, will something like 1,1k,10k ohm work? because of parts re-usage... if it is not going to work, I will add the 22ohm to the BOM 
you might be getting overly restrictive on your BoM here, 10R or 100R might be suitable. The 100R would need a bit of checking to see it doesn't mess up the loop gain in the 10's of kilohertz.
[edit fixed up some bact to front quotes!]
Home
Help
Search
Login
Register
