modern TTL/Logic-gate/74xx

[ker2x]

And how am i supposed to fail in electronic if all i have to do is to buy an FPGA dev board and write code ?

Eventually the programmers come to realize that every single line of code in a 10,000 line project is executing in parallel.  Signals 3 levels deeper are still changing state, massive things are happening on each clock pulse.  Just handing data off from one module to another has timing implications if the processes are clocked (one clock delay is typical, sometimes 2 if crossing a clock domain).  It is up to the designer to keep track of the timing of every signal in the design.  In bits and pieces, true, but everything is happening in parallel.

There is nothing in the world of procedural code that comes anywhere near to being as massively parallel as writing in an HDL.  What ?  A CPU has 4 cores and 2 threads per core?  8 things going on at a time?  That's trivial!  In HDL I can have thousands of independent processes all running in parallel, happily moving information from place to place.  Got FreeRTOS running?  Great!  But it's still just serializing.

I'm aware, that's what got me interested in FPGA in the past, years ago, until i realized it wasn't fun at all 
I'm a big fan of developing using pipelines, with one threads per pipeline. But still, it's much different than coding FPGA for sure.
The learning curve of fpga remind me of this meme :
https://aws1.discourse-cdn.com/eveonline/original/2X/9/9a395dad41a3cccfecd1346e6bc4aa48beb14442.jpg

[rstofer]

Of course I like hardware, that was my major in grad school back in '75..'76, when the 8080 was king.

One of the problems I have with learning new skills is that unless I have a project with an end goal, I won't stick with it.  I have tried several video series on C++ and Python and I get into it for a short while but burn out quickly.  The reason is two-fold:  First, I don't have an immediate need for the skill and, more important, the tutorials tell me what to do and how to do it but they don't tell me why I would want to do it.  Just because everything is an object, why should I code THIS project using THAT process when I can just do it in C or Fortran?

I would imagine that learning an HDL would be the same kind of thing.  Unless there is an immediate goal and adequate tutorials, why bother?  Frankly, it would be boring.

How about one last experiment before trashing HDLs forever?  Use Vivado to create a 74181 (and, for extra credit, a 74182 carry generator).  That's all.  Keep it simple, just 4 bits wide.  Now run the simulator (which I have never used) and see if it will do all the operations required.  I have no idea how to create the test bench that provides inputs to the device but from what I have seen, it doesn't look hard.  Somebody around here can help with that.

Since this is just combinatorial logic, I would just use toggle switches for the inputs and LEDs for the output.

I could choose to write the code using the logic diagrams on the Internet or just use a CASE statement.  Likely I would use a CASE statement based on the M input and under each branch, I would have a CASE statement for each of the 16 functions.  I might break up the Arithmetic CASE statement into two further CASEs based on the Carry input.  That would make the function quite clear.

http://www.righto.com/2017/03/inside-vintage-74181-alu-chip-how-it.html

Here's a defined goal - get an ALU to work!  Once done, this is the most logically complex part of a CPU and it works!

[schratterulrich]

Hello ker2x,
if you decide to build your project with discrete logic, you should really think carefully about which logic family you are using.
We have used LVC logic in the past to buffer a parallel RGB display interface for example. It was a typical case for unnecessarily fast logic with all the drawbacks. We used  series termination resistors on all nets and of course impedance defined traces. But as we had to route the bus thru a ribbon cable we caught some EMC radiation problems.
Finally we had to redesign the board due to EMC issues.
We then investigated different logic families and decided to use the 74AUP family. We could eliminate the series termination resistors and got very clean signal edges. Also the EMC radiation problem was gone.

some advantages of AUP
much shorter propagation delay than 74HC
low power consumption
"very good signal integrity"; relativ slow transition rate; ouput impedance near to 50 Ohm

some disadvantages of AUP
only in single/dual gate packages
supply voltage < 3.6 V

on the other side
Problems with too fast logic:
- signal reflections if not properly terminated
 see http://www.ti.com/lit/an/sdya010/sdya010.pdf for some information on unterminated signal waveforms of older logic families.
- GND-Bounce / VCC sag
 see http://www.ti.com/lit/an/szza038b/szza038b.pdf
- higher requirements for decoupling / power distribution

in short don't use LVC if not absolutely required for propagation delay
 

 

[james_s]

It is common for programmers of procedural code to look at Verilog and VHDL as just another language.  It is, and it isn't.  Yes, they are both languages but...  They're describing hardware, massively parallel hardware!

Eventually the programmers come to realize that every single line of code in a 10,000 line project is executing in parallel.  Signals 3 levels deeper are still changing state, massive things are happening on each clock pulse.  Just handing data off from one module to another has timing implications if the processes are clocked (one clock delay is typical, sometimes 2 if crossing a clock domain).  It is up to the designer to keep track of the timing of every signal in the design.  In bits and pieces, true, but everything is happening in parallel.

I don't even like to think of HDL as anything "executing" because it's really not. HDL is not a program, the instructions aren't executing, they're describing hardware using a language that superficially resembles a program.

If you have a line like:

A  <= B AND C;

That's not an instruction to execute an operation on variables, it's an instruction that says "wire signals B and C to the inputs of a two-input AND gate and connect the output to signal A". Once this gate has been "wired up" it will do its thing, it doesn't have to wait for an instruction to execute in a loop, the instruction described how to wire up the hardware.

Existing programming experience can be more hindrance than help when learning HDL because it's so hard to get out of that mentality of writing a program and start viewing it as describing hardware.

[ledtester]

If you don't want to learn a VHDL-like language, may I suggest:

https://clash-lang.org/

There's even a tutorial on how to go about building a CPU with it:

https://yager.io/CPU/CPU1.html

[ebclr]

You may have many hundreds of 74 series chips, on an FPGA, without writing a single VHL line, only drawing the schematics,

[hamster_nz]

You may have many hundreds of 74 series chips, on an FPGA, without writing a single VHL line, only drawing the schematics,

Hundreds? Nah, many thousands!

I once worked out that the small FPGA was equivalent to a breadboard the size of a garage, and a (then) large but still obtainable one was equivalent to a basketball-court sized breadboard - complete with 100s of impossibly accurate wire-running gnomes.

The problem with schematic entry is the additional information required. Rather than "C <= A AND B", where A B and C are 8-bit wide buses, you have the following data to manage:

This is an AND gate "AND_1", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).

his is an AND gate "AND_2", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).

his is an AND gate "AND_3", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
....
and so on for eight gates required to AND two 8-bit values.

So rather than a few lines of HDL you end up with maybe 120 to 300 bits of data (all the 'x's and 'y's and 'r' and names and labels)  that have to be managed manually - sure most of these are mouse clicks and moves, but it still is a lot of information that has nothing to do with the actual function of the design, only it's presentation to the designer.

If drawing schematics is your thing, than this might scratch your itch and keep you busy on a rainy day, but it is too  much like doodling in the margins of a notebook...

But by all means start with schematic entry - you will quickly get frustrated by it you will want the "better way" that a higher level symbolic representation offers.

[ebclr]

I for sure do the HDL way, but the OP wana buy and solder chips, this will be better than that

[rstofer]

It may be worth the time to block out the design and count the chips and interconnects.

[ker2x]

It may be worth the time to block out the design and count the chips and interconnects.

This is the first time i try an "hardware first" project on my own.
Before drawing any schematic i needed to know what was available (without doing any dumpster diving to recycle old 74xx chips).
The problem of 74xx availability have been solved (74HC chips from On Semiconductor), they're not the cheapest option but they exist.

I find it funny that some Atmel ATTINY cost less than a quad OR gate.
But the cost isn't a factor anyway, the value of the finished product will never worth the money and i'm okay with it, as long as i don't have to invest tons of money upfront (and there is no need for it).
Even if i bought an absurdly overkill Zynq or Artix-7 fully featured dev board.

But since the whole 74xx problem have been solved everyone is telling me to use an FPGA instead.
I may be stuborn, but not stupid (hopefully?) and you know more about electronic than i do and ever will.

The design will depend on the capabilities of the hardware.
If i did it out of logic gate, the CPU would have been a subset of a 6502 + UART.
On an modern FPGA i could have a full 6502 or Z80 (it have been done countless time) and still end up using only a few % of an entry level fpga (spartan, artix).

It's been only a day so i can't decide what to do yet.

BUT, i have an idea 
(of course i may change my mind again)

The original plan was :
- build the cpu using logic gate
- emulate the rest of the computer, and test the subcomponent of the CPU, using a microcontroller

The new plan may look like this :
- Buy a fully featured fpga dev board (a entry-level one, not one with RF transceiver and 8x 10G ethernet, they are super expensive and useless to me)
- Learn and use this fpga, instead of a microcontroller, for the testing and emulation of the non cpu part of the computer.
- Once done, build the cpu out of logic gate, or build it in-FPGA. Or both.

I have yet to decide if i use an FPGA or a (C)PLD, as i mentioned earlier i misunderstood what a (C)PLD was and therefore know nothing about it.

By the way, i'm pretty sure there will be a massive problem interfacing FPGA and 74xx, right ?
noise, impedence, timing, voltage, younameit ?

[ker2x]

It's been only a day so i can't decide what to do yet.

Huh... this sentence may lead to a grave misunderstanding. 

It's not like i woke up monday morning and decided to do this.
It's been on my mind since much more time than that and i already have some 100% software project in progress.
And i played with developing interpreters, OS, computer design, since a long time.

[ker2x]

Would you suggest a zynq or an artix ?
i probably have no use for the ARM core but... just asking.

edit : i forgot that their website was an absolute nightmare in the past and didn't get any better.

[rstofer]

Are you aware of the Ben Eater project?
https://eater.net/8bit

I worked on that for a while until I lost interest in making breadboard jumpers.  Nevertheless, it's a pretty cool project and demonstrates quite nicely how a CPU actually works.

As I said earlier, this is my favorite board:
https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/

Given the 100T version, I can fit a 64k word 16 bit RISC processor in there with the following utilization


BlockRAM 24%  <--- there's quite a bit of BlockRAM left for things like disk buffers and such
IO       25%  <--- I am using a lot of IO to drive the gadgets on the board but I can only do that once
LUTs      1%  <--- the fundamental logic blocks
FFs       1%  <--- flip flops
BUFG      3%  <--- used for clock nets.  I didn't deliberately instantiate any BUFGs in this design


In other words, a fairly complete RISC processor (the LC3 project) rolls around like a BB in a Bowling Alley.  I can add features like disk IO and never put a dent in the use of LUTs and FFs.  This thing is a virtual dumpster full of chips.

ETA:

Suppose I do decide to add an SD card.  I could build the controller in logic or I could plunk down another RISC core (with much less BlockRAM) and write the driver in C.  All I would need to do is add a DMA system to share the BlockRAM between the main RISC core and the SD controller.  I might even be able to use the dual-port feature of the BlockRAM and keep the CPU on one side and all of the IO devices on the other side.  This means the DMA controller/channels are on just one side of the BlockRAM and the CPU can run uninterrupted by memory collisions.  I could also instantiate a Xilinx core and use their tools to port an entire network stack.  And STILL the main CPU could run uninterrupted.  And I haven't even gotten to the bit about using the DDR as static RAM with code provided by Digilent.

I have a lot of FPGA boards (for a hobbyist) and most of them feature a lot of gadgets.  I don't really like the naked boards because development is slowed while I hack in some LEDs and displays.  I consider the gadgets as far more important than the chip itself.

I don't have a Zynq board and I haven't found a need for one, yet.  Obviously, using the ARM core to drive all the IO devices for a low end RISC core makes no sense at all.  Just buy a Raspberry Pi 4 and be done with it.  One day I may find a reason for that board and, sure enough, one will wind up on my bench in a few days.

Artix 7 seems to be the chip of choice at the moment.  Older versions (Spartan II, Spartan 3 and up to Spartan 6, I believe) need to use ISE 14.7 as the toolchain and this is obsolete and not really supported.  It is far better to pick a chip that is supported by Vivado.  Within a family, BlockRAM is the biggest discriminator.  You need all the BlockRAM you can get.  If the incremental cost isn't a show stopper, get the biggest device available.

I didn't mention any of the non-Xilinx vendors.  I simply don't have any experience with them.

[ker2x]

Are you aware of the Ben Eater project?
https://eater.net/8bit

Yes, i follow his youtube channel

[ker2x]

As I said earlier, this is my favorite board:
https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/
Given the 100T version, I can fit a 64k word 16 bit RISC processor in there with the following utilization

Perfect, it was in my wish-list already so i just ordered it.
I'll receive it in 2 or 3 days.

The other one in my wishlist was this one https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/
Cheaper, smaller fpga, no DDR, no audio.

About DDR, i had a board with DDR, it seamed to be really difficult to use.
Digilent have a github repo with this : https://github.com/Digilent/Nexys4DDR
i hope it's what i think it is

[rstofer]

I have that Basys  board as well.  It's pretty nice but the 35T device is a lot smaller than the 100T device.  I hope you selected the 100T variant rather than the much smaller (in terms of BlockRAM) 50T device.  Bigger is better - always!

ETA:  You will find the DDR component under Additional Resources on the original Nexys 4 DDR board page:

https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start

I think this is going to take a bit of studying.  I have never used it.


 

[ker2x]

I hope you selected the 100T variant rather than the much smaller (in terms of BlockRAM) 50T device.  Bigger is better - always!

Of course 

[rstofer]

Perfect, it was in my wish-list already so i just ordered it.
I'll receive it in 2 or 3 days.

Well, I guess that settles the chip vs FPGA question!  I think you'll like the board.  You need to install Vivado and then follow the Yellow Brick Road at Digilent to install their board files.  This is an important step.  You don't want to design to the chip level, you want to design for the board so, when you create a project, you will select the Boards tab and find your board in the list.  Installing the files is easy to do but it is a really big deal!

So, while you wait, you might as well install Vivado and the Digilent files.  I have forgotten whether you need to install the Digilent Adept software but you might as well.  Once everything is tied together, board programming is seamless via Digilent's USB->JTAG device.  Seamless was always important to me, I really never liked using JTAG dongles even if they did work from time to time.

The USB gadget also appears as a UART - this is really handy since almost every CPU project will want to talk to a PC.

As you no doubt found out, there are a lot of resources for this board (and its predecessor, the Nexys 4 DDR) at Digilent.  It might be worth looking around for tutorial projects.

When I program a project into the board, I program only the FPGA, not the platform flash.  That way, on power up, I get the crawling snake, not the remnants of some program I was previously working on.

[ker2x]

I realize there might be a problem : https://www.amazon.fr/gp/product/B0714MKJ4H/
1) the digilent product description on amazon.fr are garbage (on all their product)
2) the picture show a nexys A7
3) the title say Nexys 4 DDR, which is discontinued

Both board are nearly identical according to digilent. I can't even find the difference.
I'm wondering what product i'll get 

The description also say Nexys 4 DDR.
Well, if they are the same, i don't mind. If there is a difference i don't like i can send it back saying the picture was wrong and the description unreadable.

The wiki say : "The only difference between the Nexys A7 and Nexys 4 DDR is the addition of the Nexys A7-50T variant of the Nexys A7, which has a smaller gate array. The Nexys A7-100T variant is functionally identical to the Nexys 4 DDR."

[ker2x]

Perfect, it was in my wish-list already so i just ordered it.
I'll receive it in 2 or 3 days.

Well, I guess that settles the chip vs FPGA question!  I think you'll like the board.  You need to install Vivado and then follow the Yellow Brick Road at Digilent to install their board files.  This is an important step.  You don't want to design to the chip level, you want to design for the board so, when you create a project, you will select the Boards tab and find your board in the list.  Installing the files is easy to do but it is a really big deal!

So, while you wait, you might as well install Vivado and the Digilent files.  I have forgotten whether you need to install the Digilent Adept software but you might as well.  Once everything is tied together, board programming is seamless via Digilent's USB->JTAG device.  Seamless was always important to me, I really never liked using JTAG dongles even if they did work from time to time.

The USB gadget also appears as a UART - this is really handy since almost every CPU project will want to talk to a PC.

As you no doubt found out, there are a lot of resources for this board (and its predecessor, the Nexys 4 DDR) at Digilent.  It might be worth looking around for tutorial projects.

When I program a project into the board, I program only the FPGA, not the platform flash.  That way, on power up, I get the crawling snake, not the remnants of some program I was previously working on.

I started installing vivado even before ordering the card 

It pretty much settle the chip/fpga but not so much.
I still have the option to design the cpu on chip but : i probably won't, and i'll implement everything in fpga before doing an eventual chip version. There is a VGA port after all, i MUST use it 
This board probably doesn't have enough I/O for interfacing with a homebrew CPU anyway. I could buy, later, a cheap nano board with no accessories, only the fpga and tons of I/O if i really want it. Something like this : https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/
But i learned my lesson. i have a board like this (with a Spartan-6) and it's NOT a good way to learn 

[rstofer]

I liked the older Spartan 3 Starter Board with 3 ea 50 pin edge connectors.  I used one connector for a logic analyzer interface (32 channels) and the one on the right for a Compact Flash board.  That LA is the only way I ever got the system to work.  The Vivado ILA will do it even better!
https://store.digilentinc.com/spartan-3-board-retired/

I eventually migrated my IBM 1130 to a Nexys 2 board.  It's very expensive for what it is but at least it had an edge connector for the Compact Flash board (and a 4 channel FTDI UART<->USB board).  This was back when the Nexys 2 was the top of the line...
https://store.digilentinc.com/nexys-2-spartan-3e-fpga-trainer-board-retired-see-nexys-4-ddr/
https://www.digikey.com/product-detail/en/ftdi-future-technology-devices-international-ltd/FT4232H-MINI-MODULE/768-1031-ND/2027253

I built a logic analyzer out of the small version of the Starter Board:
https://www.sump.org/projects/analyzer/

PacMan is built on another Nexys 2 board just because I had it sitting around.  The T80 core (Z80) at OpenCores.org is excellent for retro arcade games (that used a Z80) and for running CP/M on a Compact Flash.
https://opencores.org/projects/t80


There are 6502 cores at OpenCores.org  Among others:
https://opencores.org/projects/cpu6502_true_cycle

[james_s]

This is the first time i try an "hardware first" project on my own.
Before drawing any schematic i needed to know what was available (without doing any dumpster diving to recycle old 74xx chips).
The problem of 74xx availability have been solved (74HC chips from On Semiconductor), they're not the cheapest option but they exist.

It's because they're a niche specialty part today, AVR microcontrollers are sold by the many millions, 74xx parts are probably at least an order of magnitude smaller market.

[rstofer]

That Gadgetory site has a lot of component kits for the tutorials by PyroEDU
http://www.pyroelectro.com/edu/
https://gadgetory.com/index.php?route=product/category&path=66

This might be a very acceptable learning program which, by being more up to date, is somewhat easier to approach.  There are lab examples using the component kits from Gadgetory along with DVDs for each of the major sections (I don't know if they are just duplicates of the YouTube videos).

I have only watched about 1-1/2 videos but I'm reasonably impressed.  A beginner would be a long way down the path after completing this series.

Lab examples are probably the best way to learn electronics.

I'm going to spend a bit more time on this site!

[jmelson]

Thanks to my painful experience with FPGA i have a rough idea of the importance and difficulty of timing.

Well, I don't do "cutting edge" projects where I need to get every last ns out of an FPGA.  On the other hand, I did do a project where we had a bunch of 32-bit counters running at 150 MHz on a Spartan 3AN FPGA, which is a pretty old part.  No problem whatsoever getting that to compile and work.

So, any place I need about 3 - 10 TTL chips worth of stuff, I use either a 9500XL or CoolRunner II CPLD from Xilinx, for about $1 - 2 each.  For more than about 10 TTL chips equivalent, I use a small Spartan 3A for about $13.  Basically, if it simulates, it works, period!  And, if it doesn't simulate, it is because I am lousy at writing VHDL.

Jon

[rstofer]

Whether an HDL or a procedural language, the only way to really get a handle on it is to write it.

This book (free) will help:

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

Page 93 is where the Finite State Machine coding really starts.  Note where the author pre-assigns the output.  Page 95, first bullet, explains why.  This is a CRITICAL concept!