LM324 Power Supply with variable voltage and current

[xavier60]

If a simple solution can't be made to work, this is certain to.

[iMo]

I would go with the zener and LED version 2 (updated above), as the compare will be "sharper", imho.
An Led and 3.9-5.6V zener.
Below with Blue (top) or Red LEDs.

[mike_mike]

I modified into my simulation.

Later Edit: added updated file.

Later Edit 2: updated file.

[iMo]

You may remove the soft start when the Vcc undervoltage lock is used.

The CC set voltage buffer - in a different thread we messed with a PSU design it showed to me this kind of CC sensing requires an low impedance source for the compare divider. It could be the whole "CC precision" is not great here, therefore it may work without the buffer. You have to try and measure.

[mike_mike]

Updated file.

You have to try and measure.

Do I have to try in the practical circuit ? Or in the simulation ?

[iMo]

Try to make a few simulations with different Rloads, Vout and Icc settings.
Also try to add some output capacitance (with ESRs) to see what happens with larger capacitive loads (up to 2000uF for example).
You may make the 1ms load switch pulse longer in the simulation such you see the whole event with smaller loads and larger caps, like

PULSE(0 1 0.01 10n 10n 10m 50m)

PS: also do use the 7812 instead of V6 there, of course.

[Kleinstein]

This circuit should not need the buffer for the CC set value. It would only effect the linearity of the setting a little, but pots are not that linear anyway.

For most of the simulations V6 instead of the 7812 should be OK.

I would still consider 1 diodes parallel to R30 to allow for a reduced R29 and thus drop.

For further testing in the simulation (e.g. load tests, like 1 A  - 1 mA - 1 A) one can use the spice current source as a load. This is easier than the switch and resistor and does not include the resistor as a helping load.

The current "source"  can also be used in an AC mode simulation to look at stability: the output voltage than gives the output impedance (in ohms, as the source is 1 A for 0 dB). This way one can see the possibly critical loads (capacitance) without separate runs.

[mike_mike]

Here are the results with resistor load, and the .asc file.

Please have a look at the screenshots and tell me what you think...

[mike_mike]

New tests, with the CC buffer removed.
I am also attaching the .asc file.

Please have a look at the attached screenshots and tell me if the results are good.

[Kleinstein]

The simulation results so far look good. However they are only the CC to CV and CV to CC transitions.

One should at least simulate a few more normal load transients in the CV mode. Something like a 10 mA - 1 A - 10 mA cycle. Once with just the load and once with an extra capacitor like 1000 µF with some 5 mOhms ESR.  The extra cap case would be about the worst case load. One should have the CC limit at some 1.5 A and maybe some 1.1 A for a test.

[xavier60]

I am curious to see what voltage the Base voltage of Q1 needs to go up to for a 3A load.

[mike_mike]

@xavier60 Please find attached the voltage (green color) for the base of Q1. Color blue = output current.

@Kleinstein I will come back with the results...

[mike_mike]

@Kleinstein
The results:
1. Resistive load 24,25
2. Capacitive load 26,27

Please have a look at the results and tell me if they are good.

[xavier60]

@xavier60 Please find attached the voltage (green color) for the base of Q1. Color blue = output current.

@Kleinstein I will come back with the results...

That shows that the output stage should have plenty of gain.

[mike_mike]

What else should I test next ?
Are the last 4 screenshots good or not ?

[Kleinstein]

@Kleinstein
The results:
1. Resistive load 24,25
2. Capacitive load 26,27

Please have a look at the results and tell me if they are good.

The resistive load looks Ok, as far as one can see it. The scale is rather poor, as the interesting part is some +-500 mV around the set voltage. No need to show multiple periods.

For the capacitive loading there was a misunderstanding: the capacitor should be fixed connected to the regulator for the test, and only the current switched (ideally with a current source element, but the resistor and switch version is also acceptable, though not such a strict test).

[mike_mike]

For the capacitive loading there was a misunderstanding: the capacitor should be fixed connected to the regulator for the test, and only the current switched (ideally with a current source element, but the resistor and switch version is also acceptable, though not such a strict test).

Like this ? 28.png

Later Edit: this is with resistive load: 29.png

[iMo]

Zoom in at the rising edge (blue) 28.png - it looks like ringing there..

PS: when you remove R4 and C4 you will get nice ringing with aprox 457us period. It comes from R2C1 in CV comp. Needs to be fine-tuned somehow (or to find values as a good balance between resistive and capacitive loads).
In the meantime increasing C4 to 4n7 helps.

[Kleinstein]

The case with a 1000 µF low ESR cap is a really difficult one - close to the worst case. So in this case some ringing is not a problem if it is not too much. One might still tweak the circuit a little, but there is no need to avoid ringing all together.

The load response without the extra capacitor looks good.

[iMo]

This is without R4 C4 input CV divider comp.
28.png setting.

Sure a difficult load. Curious how to fine-tune that response.
It is sensitive to R2C1.

[iMo]

 

[xavier60]

Some minimum load should reduce the bouncing.

[Kleinstein]

For tuning I would look at the output impedance, with a current source (sink) in AC mode.

Those triangle like oscillations are a special case that includes some wind-up / nonlinear effects.

Some limitation of the wind-up can help. A good stability in the linear range case is a good starting point though. For the wind-up effects I see only the transient mode simulations.

A minimum load can help, but the effect is limited if a large cap is present.

[mike_mike]

I understood that there is a problem regarding the ringing of the power supply when powering loads.
The ringing depends on R4, C4 and it is sensitive to R2, C1.
What would be the next step in solving this problem ?
Making experiments in LTSpice using different values for R2 and C1 should solve the problem ?

[iMo]

Output impedance:
Updated