Huh, well, okay then...
Hi everybody!
Let's talk loads, then.
Electronic, not the fecal kind!?...
I won't exactly run through the complete design process here, but highlight some important points.
Beware one simple confusion: MOSFETs in [voltage] saturation (Rds(on) dominant), are trivial. Rds(on) has positive tempco, as long as all transistors are firmly on at the same time, or completely off, no issue. There's still dynamic current sharing issues, and switching needs to be synchronized, but that's mostly a short-term problem, and not a big deal to solve.
MOSFETs in linear operation (Vds > Rds(on) * Id) ARE NOT trivial, and have a negative tempco. One heats up, draws more current, heats up some more, exceeds ratings... BANG!!
Some have already mentioned this, and it can be looked up in detail in appnotes and other threads. Linear operation takes a bit more finesse than switching does.
In general, transistors have negative tempco, in that input threshold falls as temperature rises. A strategy is required to use parallel devices in linear operation without runaway failure.
The simplest and most common is probably the source/emitter degeneration resistor. This reduces gm of the transistor overall (making Id vs. Vin more linear) and increases Vin with a neutral or positive tempco, so that stable operation results. It might still be NTC overall, but at a slope of 10%, 5%, whatever, a lot less than it would naked.
The downside is, you need to drop a lot of voltage for that to be the case. So it's not a popular strategy for low-voltage or wide-range loads.
I do use this technique in a high voltage load I built, which handles a 100-500V 4A operating area with just three 200W linear transistors in parallel. (That doesn't add up, of course: the remainder is handled by an array of switched resistors. A clever application of an old converter IC handles the switching.)
If low voltage drop is required, then we'll have to grapple with the tempco directly, and other device variation (in general, temperature, Vgs(th) at given temp, and gm, all differ between random devices).
The easiest way to do this, is to wrap it in an op-amp, turning it into an ideal current sink -- independent of device parameters. These CCS blocks can then be wired in parallel as required. Hence the one-amp-per-transistor architecture.
That covers device operating characteristics, then. What about limits?
It currently has 4 STP110N8F6 on it. The datasheet seems to say they SHOULD take 80v at at least 100a (give or take),
NOT AT THE SAME TIME!
There is a third rating you missed: Ptot = 200W. Together, all three describe a truncated hyperbolic operating area (or a truncated square on a log-log plot), where operating conditions must respect
all three simultaneously!So yeah, you done fuckered it good.
Well, maybe. 53V 7.5A is 400W total, and you have more than two transistors in there. But 200W is
quite a lot for a poor little TO-220...
...And yeah, transistors generally fail shorted. There may be no outward signs of failure (magic smoke, bubbling or cracked package, melted leads..), just a silent death. If sufficient, ah, propulsive energy, is available though, the short circuit can draw enough current to fuse the thing open (usually with attendant shrapnel...BANG!).
Note that they tend to go three-way short, so you can get drain voltage (or some fraction thereof) on the gate terminal in the process. The op-amps may well be fried, or questionable now.
In this case, the 1k series resistor between S and -IN, and OUT and G, are probably enough protection from the 50V supply; still, wouldn't hurt to check component specs. If it were, say, a 200V supply and load, or more, I'd think further damage very likely.
The SOA graph for these particular devices doesn't show a DC plot unfortunately, but I assumed I was still in the safe area, so I think what delivered the final blow is still the power aspect !
Warning signs: no DC SOA is no guarantee of failure at DC -- but you just don't know. At the 1ms curve, the die is just coming to temperature, but heat hasn't spread out in such a way as to cause much instability yet, so it's really nothing to go on.
Design approach: reject it. Put away the datasheet and look into the next, etc. etc. until one with adequate ratings is found.
Since we don't get an example here, I'll mention it outright: most devices (BJT and MOS alike) exhibit 2nd breakdown, where a local region of the die heats up, and guess what, Vgs(th) drops there, so it starts getting hotter, and... See where this is going?
Again, all transistors are inherently unstable, it's just a question of when, of how much. You can have an unstable device, but run it at low power so that the conductivity across the die and mounting tab is dominant (silicon is a good thermal conductor, and copper is great), while the amount of power dissipated in that area is small and so too the hot-spotting, and tendancy towards hot-spotting worse. This is expressed on the SOA curve as a steeper slope; usually it's a 1:1 slope (I = P/V, a hyperbola, but on the log-log plot it's a downward-sloping straight line), but near the instability region, it can become 50, 100% steeper, or more, and the maximum power dissipation drops considerably.
Some types are more stable than others -- usually older types, with lower power density, higher capacitance for given ratings, are okay with DC up to full ratings -- but also some newer types, despite remarkable power density (SuperJunction types dominate the >300V range), the downside being, they do use smaller dies so the total power dissipation is smaller for the same switching ratings (Vmax * Imax), which may cost more per watt.
(Old types can be identified by, heh, well, presence in old databooks for one -- ye olde International Rectifier and other databooks are still good resources, including classic appnotes and such, that often go overlooked or forgotten on the internet today. Otherwise, classic families like HEXFET(R) (IR, now Infineon), or "DMOS" or "planar" something or other, and the various IRF(P)xxx(x) types and second-sourced equivalents, are typically okay. Curiously, current IRFxxx datasheets never give DC SOA, but the old databooks once did. From a design-assurance standpoint, best to avoid them -- but you can test a given sample and qualify them for use, if such testing is acceptable.)
SOA is the prerequisite. Thermal resistance is the final test. You must respect Tj(max), or -- various things perhaps, but device failure is greatly accelerated at high temperature, and some phase-change stuff happens like the plastic packaging swelling/weakening that can cause failure much more rapidly.
You need enough heatsinking, and good thermal contact, to dissipate the required power.
For a load like this, usually the drains will be tied together so a simple greased joint, bolted directly to the heatsink (assuming you don't mind the heatsink is live -- mounting on insulators is required!), will do. This maximizes conductivity between device and sink, and mostly puts the limit on the sink itself. You'll have to monitor sink temperature, and use RthJC and operating power to estimate Tj. Thermal analysis is done just like DC circuit analysis: power is current, temperature is voltage, and resistance is resistance. If we put 100W into a 0.75 K/W device (like the STP-), it should rise 75K. If Tjmax is 175C, Tc must be under 100C, and Ths less still. A limit of 80C on the heatsink might be adequate, assuming no SOA problems, and a total rating of 400W between 4 devices sharing evenly.
Against an ambient of say 30C, that's Δ50°C / 400W = 0.125 K/W total required of the heatsink. That's a pretty beefy heatsink, and even then, almost certainly needs a fan.
Heatsink can be hotter if lower RthJC is available -- use bigger devices (TO-3P or TO-247?), or use more in parallel (e.g. derate the circuit to 200W and double it up).
I then came to my senses and a bit and began analyzing. Check out these ones for example: YOU'D THINK that with a power dissipation of 1.6kW SURELY they're indestructible, but looking at the SOA graph (which thankfully DOES include a DC line this time) my test setup could've STILL killed them, because at 53v, the safe area caps off at a modest 3A, despite still being within the power dissipation figure. Correct me if I'm wrong...The whopping 4400pF capacitance may also be a problem....I'm aware of that parameter too, despite not fully knowing how to use that data in design...
Yup, IXYS (now Littelfuse) makes some pretty big devices. But you don't want HyperFET or PolarHV or whatever, those are all optimized for switching. The Linear and L2 families are however suitable for this application. This for example,
https://www.littelfuse.com/media?resourcetype=datasheets&itemid=77d02c51-2981-4873-a49f-9aa92a37d26a&filename=littelfuse-discrete-mosfets-n-channel-linear-ixt-200n10-datasheetcan consume your entire power supply, given enough heatsinking -- and it will have to be quite good to suck quite that much power out of the still relatively little footprint of that TO-264 (or PLUS247, you mount it with a spring clip, pretty convenient actually). Again, rating goes down reeeeal quick when everything else starts to heat up.
But since IRFP240 and etc. are still abundant, I don't know that I would bother.
Capacitance, hardly matters for a DC load, but you do need enough compensation (the RC across the opamp) to tame it, and you may want some maximum response time so you can do effective load step testing on power supplies, for example.
Tim
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