Implementation of input AND logic for many digital inputs

[elki]

I am wondering what would be the best strategy for identifying all pairs of coincidences using TTL signals with the duration of about 20ns each in case there are many inputs (e.g. 100). The approach with using multiple AND gates seems OK but the number of ICs increases drastically with the number of inputs signals. Is FPGA the only way to handle it efficiently?

[Andy Chee]

Is diode logic an option?



Actually, for 20ns pulses, you might have to replace the resistor with a current source to get this to work properly, if at all.

[Psi]

If LVTTL is ok you could look at a CPLD that has 100 IO pins. Bit overkill though.

You can also get really simple programmable logic chips intended for glue logic that you program by just dragging in and connecting basic gates in their GUI app. I forgot the brand/name. They are simpler and cheaper than CPLD's and easier to program with no experience. They are ultra tiny though, super fine pitch DFN. I cant recall if they come in 100 IO versions though.  But using a small number of them you could definitely build a fast 100 input NAND pretty easily and PCB would be physically quite small and cheap.

[brucehoult]

I am wondering what would be the best strategy for identifying all pairs of coincidences using TTL signals with the duration of about 20ns each in case there are many inputs (e.g. 100). The approach with using multiple AND gates seems OK but the number of ICs increases drastically with the number of inputs signals. Is FPGA the only way to handle it efficiently?

100 inputs? So .. 4950 pairs (and outputs).

How often do these 20 nS pulses happen?

What do you plan to do with the 4950 outputs?

Perhaps what you actually want is a list of all ON signals at a given time, not their cross-product?

[elki]

If LVTTL is ok you could look at a CPLD that has 100 IO pins. Bit overkill though.

You can also get really simple programmable logic chips intended for glue logic that you program by just dragging in and connecting basic gates in their GUI app. I forgot the brand/name. They are simpler and cheaper than CPLD's and easier to program with no experience. They are ultra tiny though, super fine pitch DFN. I cant recall if they come in 100 IO versions though.  But using a small number of them you could definitely build a fast 100 input NAND pretty easily and PCB would be physically quite small and cheap.

Thanks, I was indeed starting looking at CPLD options in addition to FPGAs.

[elki]

Is diode logic an option?

(Attachment Link)

Actually, for 20ns pulses, you might have to replace the resistor with a current source to get this to work properly, if at all.

Looks very interesting!

[elki]

I am wondering what would be the best strategy for identifying all pairs of coincidences using TTL signals with the duration of about 20ns each in case there are many inputs (e.g. 100). The approach with using multiple AND gates seems OK but the number of ICs increases drastically with the number of inputs signals. Is FPGA the only way to handle it efficiently?

100 inputs? So .. 4950 pairs (and outputs).

How often do these 20 nS pulses happen?

What do you plan to do with the 4950 outputs?

Perhaps what you actually want is a list of all ON signals at a given time, not their cross-product?

The frequency of these pulses is rather low, of the order of 100Hz. If the given time corresponds to the typical pulse width, then, yes, the list of all high inputs happened within this window is what I would need to have.

[DavidAlfa]

A giant AND gate?
As stated by Andy Chee, a bunch of diodes will do the work, the 1n4148 has 1ns switching time and extremely low leakage currrent.
100x diodes connected to a single inverter gate, then a single "wrong" input will set/reset the gate depending on the orientation of the diodes.

[brucehoult]

I am wondering what would be the best strategy for identifying all pairs of coincidences using TTL signals with the duration of about 20ns each in case there are many inputs (e.g. 100). The approach with using multiple AND gates seems OK but the number of ICs increases drastically with the number of inputs signals. Is FPGA the only way to handle it efficiently?

100 inputs? So .. 4950 pairs (and outputs).

How often do these 20 nS pulses happen?

What do you plan to do with the 4950 outputs?

Perhaps what you actually want is a list of all ON signals at a given time, not their cross-product?

The frequency of these pulses is rather low, of the order of 100Hz. If the given time corresponds to the typical pulse width, then, yes, the list of all high inputs happened within this window is what I would need to have.

OK, so is there a specific clock pulse that tells you when to sample everything, or all 100 signals are triggers?

In the latter (harder!) case I would say that given the low repetition rate of 100 Hz, one approach would be to use 13 Parallel-In-Serial-Out 8 bit shift registers, with the parallel load of each one's 8 bits triggered by an 8-input OR gate. Those 13 enable signals would then themselves be OR'd to make an interrupt for some small microcontroller, which would then serially read all the shift register contents and make a summary. The 100-bit bitmap would be the most compact form of this information (13 bytes) to send on to wherever.

An FPGA with 100 inputs might well be cheaper than several dozen TTL chips. Certainly it will be smaller.

[elki]

I am wondering what would be the best strategy for identifying all pairs of coincidences using TTL signals with the duration of about 20ns each in case there are many inputs (e.g. 100). The approach with using multiple AND gates seems OK but the number of ICs increases drastically with the number of inputs signals. Is FPGA the only way to handle it efficiently?

100 inputs? So .. 4950 pairs (and outputs).

How often do these 20 nS pulses happen?

What do you plan to do with the 4950 outputs?

Perhaps what you actually want is a list of all ON signals at a given time, not their cross-product?

The frequency of these pulses is rather low, of the order of 100Hz. If the given time corresponds to the typical pulse width, then, yes, the list of all high inputs happened within this window is what I would need to have.

OK, so is there a specific clock pulse that tells you when to sample everything, or all 100 signals are triggers?

In the latter (harder!) case I would say that given the low repetition rate of 100 Hz, one approach would be to use 13 Parallel-In-Serial-Out 8 bit shift registers, with the parallel load of each one's 8 bits triggered by an 8-input OR gate. Those 13 enable signals would then themselves be OR'd to make an interrupt for some small microcontroller, which would then serially read all the shift register contents and make a summary. The 100-bit bitmap would be the most compact form of this information (13 bytes) to send on to wherever.

An FPGA with 100 inputs might well be cheaper than several dozen TTL chips. Certainly it will be smaller.

Any of the two simultaneously arriving pulses (i.e. within the typical pulse width) from the 100 inputs can be a trigger. Indeed, I have been also looking into registers but as you say the complexity of the board can increase significantly (i.e. the number of chips). That's why I was considering using an FPGA. Thanks a lot for the feedback!

[brucehoult]

So you REALLY don't want to trigger with just one input?  Can an event with 2 active inputs occur a very short time after an event with 1 active input? I mean much less than the 100 Hz rate? If it's anot a very very short time then I think you'd be better to trigger on any 1 input and then use software to filter out the ones that don't have 2+.

If you really have to detect 2+ active inputs before triggering then that's going to be very hard to do within 20ns.  You'd basically have to build a layer of 50 half-adders (OR for sum, XOR for carry), that feeds a layer of 25 modified full-adders, that feeds a layer of 12, that feeds a layer of 6, that feeds a layer of 3, that feeds a layer of 2 (using the left-over output from the 25 layer), than feeds a layer of 1. Basically 7 layers of gates that have to give a yes/no output before the 20ns pulses have disappeared.

Even just from a timing point of view an FPGA will be much easier. You'd need only 3 layers of 6LUT logic (in 5 input, 2 output mode)
.

[elki]

So you REALLY don't want to trigger with just one input?  Can an event with 2 active inputs occur a very short time after an event with 1 active input? I mean much less than the 100 Hz rate? If it's anot a very very short time then I think you'd be better to trigger on any 1 input and then use software to filter out the ones that don't have 2+.

If you really have to detect 2+ active inputs before triggering then that's going to be very hard to do within 20ns.  You'd basically have to build a layer of 50 half-adders (OR for sum, XOR for carry), that feeds a layer of 25 modified full-adders, that feeds a layer of 12, that feeds a layer of 6, that feeds a layer of 3, that feeds a layer of 2 (using the left-over output from the 25 layer), than feeds a layer of 1. Basically 7 layers of gates that have to give a yes/no output before the 20ns pulses have disappeared.

Even just from a timing point of view an FPGA will be much easier. You'd need only 3 layers of 6LUT logic (in 5 input, 2 output mode)
.

Thanks a lot. A tower of gates/adders is inevitable. I was trying to see what would be faster - to trigger directly on pairs or single inputs and then do software matching, as you describe. Your feedback was very useful in choosing the best path, thanks again.

[Doctorandus_P]

I had a peek at the datasheet of the 74HC133, which is a 13 input NAND gate, so you would need 8 of them to get to your 100 pin input capacity. With 6V Vcc it has a typical proparation delay of 10ns, and 28 ns worst case over the full temperature range. And you'd still need an extra gate to combine those 8 chips together. So I'm pretty sure it's not going to work with HC logic. I wish you lots of success with finding a better solution.

[brucehoult]

I had a peek at the datasheet of the 74HC133, which is a 13 input NAND gate, so you would need 8 of them to get to your 100 pin input capacity. With 6V Vcc it has a typical proparation delay of 10ns, and 28 ns worst case over the full temperature range. And you'd still need an extra gate to combine those 8 chips together. So I'm pretty sure it's not going to work with HC logic. I wish you lots of success with finding a better solution.

It might be fast enough to trigger sampling those inputs into a Parallel-in shift register. The second layer (a single gate if it's got 13 inputs) is only to trigger an interrupt for the MCU to go see what got captured.

This one has better worst-case:

https://www.ivytechengineering.com/info/stores/74ls/files/74ls133.pdf

Digikey shows plenty of 8-input gates with 5ns worst case when run on 5V with 0.8V lo, 2V hi logic levels.

[tooki]

I had a peek at the datasheet of the 74HC133, which is a 13 input NAND gate, so you would need 8 of them to get to your 100 pin input capacity. With 6V Vcc it has a typical proparation delay of 10ns, and 28 ns worst case over the full temperature range. And you'd still need an extra gate to combine those 8 chips together. So I'm pretty sure it's not going to work with HC logic. I wish you lots of success with finding a better solution.

FYI, it seems the ’133 is only made as ALS now. HC133 is discontinued.