Author Topic: Can I design a high power non-isolated buck converter?  (Read 1295 times)

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Offline AbuIbraheemTopic starter

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Can I design a high power non-isolated buck converter?
« on: May 06, 2018, 08:27:26 am »
Hi everyone,

Part of my work includes designing power supplies. Many times I come across power levels for dc-dc converter topologies; same as the one in the attached picture from Fairchild "http://www.psma.com/sites/default/files/uploads/files/10%20PSMA%20PTR%202014_10_02%20Power%20Converter%20Topology%20Trends%20Mappus%20Fairchild.pdf"

 I am wondering why different topolegies can deliver different power levels? Also can I design a 1KW non-isolated buck converter?

Thanks
« Last Edit: May 06, 2018, 08:30:19 am by AbuIbraheem »
 

Offline David Hess

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Re: Can I design a high power non-isolated buck converter?
« Reply #1 on: May 06, 2018, 08:59:21 pm »
I am wondering why different topolegies can deliver different power levels? Also can I design a 1KW non-isolated buck converter?

There are a couple of reasons.

Some topologies require a power switch with a higher breakdown voltage for a given output power.  This is especially a problem where leakage inductance adds to the required breakdown and with MOSFETs where die size is roughly proportional to the square of the voltage.  It is often more economical to use a different topology with greater complexity than higher performance parts.  Alternatively they may require excessive switching current making parasitic inductance a problem.

Some topologies produce excessive ripple current at high powers making capacitive filtering difficult.
 
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Online T3sl4co1l

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Re: Can I design a high power non-isolated buck converter?
« Reply #2 on: May 06, 2018, 09:29:47 pm »
I have no idea why they show red, blue, blue on the top row.  They're all scalable to any size.

The rest are mostly a matter of economy-of-scale.  You don't want to bother with all the hardware required of an LLC or full bridge topology.  Although, as integration becomes more common, these are more economical at smaller scales (see Power Integrations' stuff for example).

As power and especially current goes up, it becomes much more desirable to use multiple phases in parallel.  This significantly reduces input and output ripple current, and proportionally reduces the peak switching current, which helps with parasitics and snubbing, or in the extreme, makes the whole thing possible at all (where parasitics are too great, relative to the voltage, current and switching speed).

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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