How to place decoupling/bypass capacitors on four layer board

[lazarusr]

I am designing my first four layer board with dedicated ground and power planes on the inner layers. As a result, there are no power traces as such. The power and ground pins on each IC just 'tunnel' through to the relevant layer.

But that begs the question: what should I do with the bypass/decoupling caps? Should I just place them as physically close to the power pins as possible or should I be creating extra traces on the outer layers between the capacitor pins and the power/gnd pins of the IC?

I haven't been able to find an obvious answer to this. Any suggestions gratefully received.

P.S. Happy New Year!

[rstofer]

The goal is always close to the Vcc and Gnd pins.  I put mine on the underside by adding a little trace to the pads.  It really doesn't matter whether I am using 2 layers or 4 layers, getting the capacitors close to the pins is always my intent.

[KE5FX]

I am designing my first four layer board with dedicated ground and power planes on the inner layers. As a result, there are no power traces as such. The power and ground pins on each IC just 'tunnel' through to the relevant layer.

But that begs the question: what should I do with the bypass/decoupling caps? Should I just place them as physically close to the power pins as possible or should I be creating extra traces on the outer layers between the capacitor pins and the power/gnd pins of the IC?

I haven't been able to find an obvious answer to this. Any suggestions gratefully received.

P.S. Happy New Year!

The best advice is to follow the recommendation in the data sheet for the chip in question.  No recommendation?  Then it probably doesn't matter much, if at all.

Two general bits of advice: 1) large unbroken ground planes are usually a good thing (but not always -- again, what does the data sheet say?); and 2) try to route past the capacitor to reach the chip, rather than the other way around.  Overall, the goal is to keep the area of the loop comprising the chip and its bypass capacitor as small as reasonably possible.

[T3sl4co1l]

If the ground plane pair is large (covers most of the board), it doesn't much matter where you place the caps, as long as the connecting traces and vias are short (you can shorten these further by using two trace+via per pad per capacitor).

There should be a reasonably sized bulk cap also attached to the plane, of capacitance several times the total bypass capacitance value, and ESR suitable for dampening that network (which for a plane with tens of bypasses attached, will probably be in the fractional ohm range, where tantalum and aluminum polymer are most desirable, or ceramic probably with some added ESR).

Tim

[ovnr]

There should be a reasonably sized bulk cap also attached to the plane, of capacitance several times the total bypass capacitance value, and ESR suitable for dampening that network (which for a plane with tens of bypasses attached, will probably be in the fractional ohm range, where tantalum and aluminum polymer are most desirable, or ceramic probably with some added ESR).

Let me just highlight that. Shooting for the lowest ESR possible isn't always a good idea, and can lead to ringing and resonances and other crap.

[bson]

Just close to the pin like you would with a 2 layer.  Top or bottom.  Be aware though that vias (unless they're blind) will cut up the inner planes, so always inspect them in isolation once in a while to make sure you're not creating problems there.  Each time you punch down to Vcc you create a hole in GND.  Each time you punch through to GND you create a hole in Vcc (and use up a little opposite signal side real estate!).  This is different from a 2 layer board with snaking supply traces.  It's easily avoided, but also easily tripped over if you don't pay attention to it.