How do you make a good copper pour?

[ssashton]

How do you join the copper pour on top and bottom layers to  an inner GND plane, in your chosen software?

Correct me if I'm wrong, in a 4 layer PCB with an inner ground plane it is good to also add a grounded copper pour between signal traces on top and bottom layers.

In EasyEDA that I'm using, I can only connect the copper pour to the GND plane using multiple vias if it shares the net name 'GND'. Doing this has the unwanted effect of merging the copper pour with all component ground connections.

Alternatively, if I give the copper pour a different net name such as 'COPPER_POUR' I can join it to the GND plane by adding a 'component' such as a jumper pad with one net on either side. However, this only allows me to join at the jumper pad, whereas I wish to use many vias.

How do you do it?

Or... does it not matter that the pour merges with the component GND connections provided I place vias directly next to the pins?

To illustrate, this is what happens if I give the copper pour the net name GND. See C46:


This is what happens if I give a different net name, but now the vias on the outside edge are also disconnected.

[thm_w]

Normally you would use the same net name, as shown in your first photo.

In many cases it may not matter that there is no via directly beside the component pad. For important locations you have to check yourself that the via is there, eg decoupling caps, high current switching nodes, etc.

If EasyEDA has ability to disable the pour temporarily, then I would use that when laying out important traces/vias and enable it at the end.

[ssashton]

On this PCB there is an IC that specifically states in the datasheet that traces must route from VCC and GND pins to decoupling caps FIRST and then to the GND plane by vias.

If the copper pour merges the GND traces it seems like it could mess up this return path. On C61, C64 you can see the copper pour kind of 'bypasses' the capacitor around side. Is this a problem?

[exmadscientist]

On this PCB there is an IC that specifically states in the datasheet that traces must route from VCC and GND pins to decoupling caps FIRST and then to the GND plane by vias.

This sort of advice from vendors is usually overzealous. But not always. What is the IC? If it is particularly noise sensitive (sometimes meaning they screwed up or cheaped out the IC itself!), then this might be appropriate. (General best practice is actually the opposite: as much copper in parallel as possible.)

Does EasyEDA have a poly keep out tool? That is how I would normally solve this, just cut out the poly on this area on L1.

Otherwise... honestly, the top/bottom fills on multilayer boards don't help much, even when they're done well. (Of course, done badly they'll cause all kinds of trouble, but is there anything in this line of work you can't say that about?) You might skip adding them at all.

[ssashton]

Ah ha! Yes you are right about the polygon, thank you!

EasyEDA does not have a 'KeepOut' layer which I find strange coming from Eagle, but it has this 'No Solid' solid-region, lol.

If you want to cutout some copper corners, you can use “Solid Region - No Solid”, and then set different net for it, and rebuild the copper area.

The IC here is TPA3244 switching power amp. I also read the same for a 150MHz DSP I'm using. I wanted to follow the perimeter of all switching output traces with GND vias like below. It should help contain EMI, right?

[ssashton]

Also would like to ask - is there any reason I should not route that high current switching trace under the bulk smoothing cap like that? Electric field coupling in to the power lines or something?

[thm_w]

On this PCB there is an IC that specifically states in the datasheet that traces must route from VCC and GND pins to decoupling caps FIRST and then to the GND plane by vias.

No I don't see that in the datasheet: https://www.ti.com/lit/ds/symlink/tpa3244.pdf?ts=1658533776438

What it says is this:

Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path.

I would look at their example PCB layout and copy that.

[exmadscientist]

Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path.

That is not really best practice either. The planes are where the current will be flowing, so you want as low impedance a connection as possible from pad to plane. That means as many vias as possible, all in parallel! Put one on each side, put one in between, put more all over the place! However, it is still important to be close, and if you can get the capacitor pad so close to the device pad that there is no room for a via between the two, that is usually an excellent option. But if you have to have the space, for whatever reason, it will not hurt to put a via there.

I would look at their example PCB layout and copy that.

If it's a good one, sure. Sometimes they give those jobs to the interns, and you can tell.

[ssashton]

I interpret that sentence to mean connect decoupling caps close and directly to the device pins with no via between them. However I note the EVAL board is a 2 layer design so perhaps not a direct comparison to my 4 layer.

I'm probably biased because of the reading I have been doing also on the DSP chip.

(Taken from ez.analog.com/dsp/sigmadsp/w/documents/5199/sigmadsp-pcb-layout-best-practices )

Typically, we use a single 100 nF capacitor for each power-ground  pin pair. However, if there is excessive high frequency noise in the  system, an additional 10 nF capacitor can be used in parallel. In that  case, the 10 nF capacitor should be closest, and the thermal connections  should be on the far side of the 100 nF capacitor.

Then especially this advice from Dave Thib at AD to someone with noise issues on his board.

( ez.analog.com/dsp/sigmadsp/f/q-a/64763/adau1701-adc-noise---even-with-new-design )

Board under discussion. I arrowed the decoupling caps:

The SMT version is a little trickier. Do not attach the ground pins directly to the ground plane. Have them go via a trace to the caps then to a via to ground. Tying them all to one ground fill on the top layer will create a small plane that will have a lot of noise on it and this is where every pin on the part will reference to. So have the power pins go to the bypass caps only. Then to the planes.

Read this post from last week:

https://ez.analog.com/message/299867?commentID=299867&et=watches.email.thread#comment-299867

[Siwastaja]

Just ignore that 10nF|100nF bullcrap even if it seems to come from a reputable source. SRF is meaningless, only as low as possible supply impedance over as wide as possible frequency spectrum matters, and you get that by using largest possible value of C in smallest possible package (minimum ESL).

Paralleling two different values starts to matter when you need so much C that you need to go to large package size and place that further away.

10nF|100nF hardly ever makes any sense because you can get the 100nF cap in the same package (smallest you can handle, likely 0402 or 0201 if you feel like it) as the 10nF cap, and can place the single chip in the prime spot right next and between the power pins.

10nF cap would have SRF at higher frequency but if you look at the absolute value of Z, it will be roughly equal at that SRF for the two parts (despite 100nF parts being "over" SRF). In other words, the 10nF and 100nF MLCCs perform the same at high frequencies, but 100nF performs better at low frequency side. Obviously, paralleling two parts at all improves the things, especially if you are adding more vias while at it. But they could have been just 2 x 100nF for simpler BOM, and avoiding risk of oscillations which are sometimes seen when paralleling different MLCC values.

But the AD's picture really explains it all: the 100nF part is drawn physically larger than 10nF, go figure. So in this fabricated example, paralleling the parts can be beneficial, but the actual solution would have been to just use a 100nF part in that 10nF footprint.

The concept is valid, and paralleling a 4.7uF tantalum in 1206 with 100nF MLCC in 0402 makes perfect sense and is done with the AD example layout, but the devil is in the details, and the fact you should go 1000km/h with an airplane does not mean you should go 1000km/h with a car.

[ssashton]

using largest possible value of C in smallest possible package (minimum ESL).

Yes I found a paper that explained very clearly the series inductance of capacitors is nearly all down to the package or leads. I can't find the paper now - anyone know which it was?

The main reason I posted that part is for the image which shows traces to the caps and where the vias are placed to the pwr and gnd planes.

[ssashton]

I found it! Parasitic Inductance of multilayer Capacitors

[Terry Bites]

Specify thermal reliefs on the pad types you dont want to drown.
Its your choice.
Specify width of the ties (spokes). Which can be zero.
https://docs.easyeda.com/en/PCB/Copper-Pour/index.html