n-Channel JFET characteristics

[khatus]

In the above picture why it is written "negative voltage of -1 V has been applied between the gate and source terminals for a low level of V_DS".My question is wht happend if we use  high level of V_DS??
This line is not clear to me?

[magic]

At low Vds the FET is in its ohmic region and Ids increases proportionally to Vds.
At high Vds the FET is in its saturation region and Ids is roughly constant regardless of Vds.

What they mean is that the transition from ohmic region to saturation happens at lower Vds when Vgs gets more negative.