Greetings again. So i gave it a try. I needed just one trace on another layer. Layer 2 is GND, Layer 3 in 2V8.
Yes, right i did not length-match but ... the whole pcb is 2" x 1" large, the traces from the Imagesensor are <<5 cm which is < 200 ps. In comparison the Clock is 24 MHz max.
All passives are 0603 except the 1uF (0805), the two 22uF (0805) and the inductor (1210). The crystal is now smd 3.2mm x 2.5mm.
Very thin traces were only used when necessary.
Good effort!
The long trace wrapping around the SOIC pad, I think I would've just routed straight line; two vias added, who cares, shorter trace length.
I think the bypassing and vias I would've done slightly differently, just more consistently really I think -- the QFN20? is fantastic, lots of grounds and vias and bypass caps right there. The FPGA, the top-right pins (the two mismatched caps) have lots of vias, more than needed really, but well bypassed and tied to plane. The other four bypasses (or pairs) are weaker, with only 1-3 vias each.
Hrm, I guess it hasn't been mentioned yet, but a TVS on the USB would be a good idea -- deals with hot-plugging the +5V, which the bypass cap can multiply and may not be the healthiest for the regulator or whatever's wired to the header. Can be a pass-thru type that includes filtering, series resistance and pull-up/downs for the USB pair too (if the USB interface needs it; obviously not in this case(?)), or just the one diode.
Of course ESD protection, and series resistors, should be placed on the FPGA-to-header traces, if employing this degree of hardening. Maybe ferrite beads or other filtering too, suitable for application. Not really important until it becomes a quantity product, in which case those headers might disappear anyway.
The nearly single layer layout gives an even more interesting potential, that it could be 2-layer; again the JLC limitation pops up, but there are other and better fabs out there, come on...
In that case, the 2.8V can be routed point-to-point on the bottom (mostly), and the
ample bypass caps will cover things just fine. One or two lossy bulk caps should be added at the end of the 2.8V route, to terminate the PDN. Top and bottom ground poured and stitched.
Also with a 2-layer design, I think I might prefer to put more signals on the bottom side, at least just for escape -- that way the top copper, and +2.8V, can have better access to power pins. The added trace length is inconsequential.
Alternately, or, probably jointly, really: bypass caps can be removed, for example the bottom three VCC pins on the FPGA can probably all run from the same subnet with just one cap shared between them, and similarly for the top group. The supply ripple would increase only marginally (unless I'm very wrong with my guess at current draw of these chips!), and that can be dealt with, externally, by putting extra filtering around the I/O (USB and headers?). A cost optimization that's rare enough in production, but likely doable if it were to come up.
0402s (or smaller) would of course also come up in production, and yeah, anyone who's going to charge more to assemble cheaper components, they just don't win the quote, duh.
Also, er... the lack of designators (silk), which makes talking about this rather difficult!
(Unless that was just turned off for clarity? Except kinda not, y'know?, but whatever.)
Tim