First 4 Layer PCB: Traces on each layer a good idea?

[soFPG]

I am currently designing my first 4 layer PCB and I am not really sure how things are done.
The project comprises a switching buck converter, an 8-bit uC, Lattice MachXO2-FPGA (32 pins) and a low end image sensor (BGA with 20 balls).
The main reason why I need 4 layers is the smaller track width from JLCPCB (routing the BGA is not possible with 5mil traces). Otherwise, this could probably be done in 2 layers.

So, this is my layer stack:

1: Traces + GND plane (but mostly traces)
2: Traces + VCC plane
3: Traces + GND plane
4: Traces + GND plane (but mostly traces)

Does this sound like a good idea?

[EEVblog]

Yep, that's a typical stackup.
As a general SMD routing rule you try and route everything you can on the top layer and then the rest is ground and power. Misc traces go on the bottom layer.
4 layers is a luxury here, but as you say, needed for the tighter trace width tolerance for a chosen manufacturing service.

[Wilksey]

Yes, that stackup is fine, sometimes you can switch the GND and VCC plane so layer 2 is GND, but in your case it wouldn't matter.

I would say keep the inner layers clear so you have a continuous GND + VCC plane, route main signals at the top, and others that won't fit at the bottom, but try and keep all clocks, power etc "sensitive signals" to the top if you can.

If you have top and bottom fill of GND make sure you drop enough VIAs to stitch the planes together, don't go crazy and pepper the board with them though!

I've done this for years and most of my production boards work fine and pass EMC (I say most as those were the ones I was allowed to finish, but that's another story!).

[OwO]

Better stackup would be:
1 - traces + ground fill
2 - solid ground plane, no traces
3 - traces + ground fill
4 - traces + ground fill
You want at least one completely solid plane because otherwise you need to analyze the stitching on the entire board to ensure no unintentional slots.
Power planes are useless on 4 layers, and decoupling is best done by placing a large valued MLCC directly below every power pin on each IC.
On a 4 layer board the planes are very distant, and so stitching is extremely important! With a power plane you need a capacitor at every stitching point, and the stitching is very imperfect because of the via distance to the capacitor.

[EEVblog]

Better stackup would be:
1 - traces + ground fill
2 - solid ground plane, no traces
3 - traces + ground fill
4 - traces + ground fill
You want at least one completely solid plane because otherwise you need to analyze the stitching on the entire board to ensure no unintentional slots.
Power planes are useless on 4 layers, and decoupling is best done by placing a large valued MLCC directly below every power pin on each IC.
On a 4 layer board the planes are very distant, and so stitching is extremely important! With a power plane you need a capacitor at every stitching point, and the stitching is very imperfect because of the via distance to the capacitor.

Before the OP runs off and changes it, look at OwO's profile text that says "RF Engineer" 
The OP isn't even remotely close to needing anything like that.

[soFPG]

Thanks everyone for such detailed and helpful replies 

With a power plane you need a capacitor at every stitching point

What is the theory behind that?

The OP isn't even remotely close to needing anything like that.

Haha, yes. Highest frequency is 24MHz input clock for the image sensor.

Power planes are useless on 4 layers

I don't know yet, but I could imagine that additional power traces (which is the consequence for not having a separate power plane) would clutter the top layer?

[OwO]

With a power plane you need a capacitor at every stitching point

What is the theory behind that?

A power plane can't be shorted to ground of course, so capacitors are needed to stitch them to ground.
FPGAs typically require many supplies, so you have many power networks to route. You can simply route them on the layer where your power plane would have been. You can use a local Vccint plane in the area under the FPGA, but remember it has no decoupling capability (on 4 layers) and you WILL need a capacitor for every single Vccint ball. On 4 layers the "power plane decoupling" that others here talk about so much does not really exist, and under the BGA all the planes are like cheese - each via creates a big hole in it, which means there is very little left of the inter-plane capacitance. The "power plane" under the FPGA is just a network of some thin traces and must be treated like such.

[Siwastaja]

Power plane is questionable - in the typical 4-layer prototype process, it offers quite little plane capacitance. So despite being plane, it acts similarly to a thick power trace. You need bypass caps anyway. And as OwO demonstrates, where the plane matters (right under the components), it's pierced by the vias and isn't much of a "plane" anyway.

So, routing power as thick traces, or local fills where this is easier, leaves you more routing opportunities in the same layer as you don't need to "waste" a full layer for power fill.

For example, if there are no power pins on one edge of the FPGA, you can use a partial fill on the "power" layer, and then use the same layer for routing from the pins on the side with no power pins.

Try to do all routing (signals and power) on 3 layers so that you can leave one layer for a complete GND plane. If you really must have 4 layers for routing, do only short routes on that one layer, so that there are no large gaps on the ground fill. Having only small gaps means via stitching is non-critical. The rest 3 layers can be routed full of traces, then.

This "full ground" layer would usually be next to the top layer. So this will be your "I'm not touching this unless I feel like I have to cheat, and then I'll touch it just a little bit" layer.

Finally remember, more layers means everything should be getting easier. With a 2-layer design, you could be really struggling to get good loops for return currents. With 4 layers, if you can dedicate one layer to full GND that is, you don't need to think about this much at all, you always have access to the optimal path through a via; and you STILL have 3 layers left to do whatever routing, 2 of which aren't even hindered by the top-layer component placement. This should allow quite complex routing work already.

[soFPG]

Wow, seriously, this is so helpful!

I tried routing the critical paths yesterday and it just looked awful (probably also had some component placement issues) so I thought I need some help with this and un-routed everything.

I think I can start a second approach now 

[tooki]

What about dual supplies for op-amps? Is to better to dedicate a layer to each rail? Or just do a power layer with traces? Or something else? Is there even any potential advantage to doing a 4-layer board for things like audio? (And if so, what’d be the best stack-up, in terms of performance and noise rejection?)

[Bassman59]

What about dual supplies for op-amps? Is to better to dedicate a layer to each rail? Or just do a power layer with traces? Or something else? Is there even any potential advantage to doing a 4-layer board for things like audio? (And if so, what’d be the best stack-up, in terms of performance and noise rejection?)

Analog audio is easily done on two-layer boards, with a bottom ground plane and traces on top. The rails are just traces, though parts placement helps ensure that your power trace routing is rational. Certainly jump to the bottom layer for traces as needed.

For something like an ADC/DAC board with analog and digital, four layers makes your life a lot easier. Top and bottom are for traces, layer 2 is a ground plane, and layer 3 is for power. For your power layer you can put pours for the rails where you need them.

[soFPG]

Any opinions on this? Tips & tricks are very much appreciated.

No ground planes yet. Traces on Layer 1, 3 and 4.

[tooki]

What about dual supplies for op-amps? Is to better to dedicate a layer to each rail? Or just do a power layer with traces? Or something else? Is there even any potential advantage to doing a 4-layer board for things like audio? (And if so, what’d be the best stack-up, in terms of performance and noise rejection?)

Analog audio is easily done on two-layer boards, with a bottom ground plane and traces on top. The rails are just traces, though parts placement helps ensure that your power trace routing is rational. Certainly jump to the bottom layer for traces as needed.

For something like an ADC/DAC board with analog and digital, four layers makes your life a lot easier. Top and bottom are for traces, layer 2 is a ground plane, and layer 3 is for power. For your power layer you can put pours for the rails where you need them.

Ok cool, thanks! The 2-layer as you described is pretty much what I’ve been doing. If/when I get to the mixed boards like you describe, I’ll keep that in mind.

[T3sl4co1l]

Well, highest frequency will be on the order of 100-400MHz, maybe more, depending on the slew rate of pin drivers.

Maximum frequency IS NOT the fundamental frequency of a given signal, it is defined by the risetime of the edge.

Tim

[EEVblog]

With a power plane you need a capacitor at every stitching point

What is the theory behind that?

A power plane can't be shorted to ground of course, so capacitors are needed to stitch them to ground.
FPGAs typically require many supplies, so you have many power networks to route. You can simply route them on the layer where your power plane would have been. You can use a local Vccint plane in the area under the FPGA, but remember it has no decoupling capability (on 4 layers) and you WILL need a capacitor for every single Vccint ball. On 4 layers the "power plane decoupling" that others here talk about so much does not really exist, and under the BGA all the planes are like cheese - each via creates a big hole in it, which means there is very little left of the inter-plane capacitance. The "power plane" under the FPGA is just a network of some thin traces and must be treated like such.

This is a tiny piss-ant FPGA, it hardly needs belt'n'braces decoupling.
Official Lattice recommendations:
https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/PT/PowerDecouplingandBypassFilteringforProgrammableDevices.ashx?document_id=8374
0.1uF per device pin + a bulk 1uF/10uF nearby.
The chip only has 2 VCC power pins on a single rail.
This is bread and butter stuff, no need to consider anything fancy at all.
I'd have a single 1uF bypass cap for the entire chip. Maybe a 2nd one for the IO power pins.

[EEVblog]

Any opinions on this? Tips & tricks are very much appreciated.
No ground planes yet. Traces on Layer 1, 3 and 4.

Those bypass caps are all wrong. The traces are way too long. It's like you places them in the wrong rotation around the chip and then just routed them because that's what it said to do.
EDIT: Oops, I mistook the image sensor for the FPGA. The FPGA is a QFP and the image sensor is the BGA. So I was talking about the image sensor bypass caps here.

I might record a 2nd channel video reviewing this, as I think this layout could lead to some good discussion.

[soFPG]

Those bypass caps are all wrong. The traces are way too long.

Thank you. Now after looking at it again I notice that those traces are indeed very long and that the placement is bad.

I'll try that again.

This is a tiny piss-ant FPGA, it hardly needs belt'n'braces decoupling.

Yes, it's a Lattice MachXO2-1200.

0.1uF per device pin + a bulk 1uF/10uF nearby.

Okay, I forgot that 1uF.

Maximum frequency IS NOT the fundamental frequency of a given signal, it is defined by the risetime of the edge.

I almost forgot that. I was told the same statement before in another post. Furthermore, the fast rise times of FPGAs could lead to some problems on the receiver side (e.g. the image sensor).
One mentioned solution was to use ferrite beads for each pin (if I remember correctly). I don't know if this is really necessary here.

[T3sl4co1l]

Ferrite beads for short, on-board signals aren't so important.  Can be a very good idea for off-board signals though.  Even breadboarding SPI over 50cm leads can find problems with signal quality.  YMMV.

Tim

[Siwastaja]

I'd change to a smaller passive case size. Are those 0805 or what? The difference between the image sensor/FPGA parts and their decoupling caps is just massive. If you can handle soldering the small chips, you can definitely handle soldering 0402 caps. Then you can get them closer, right next to the pins. Larger parts usually don't fit close, forcing you to do longer routing, which is bad for power integrity, and also wastes routing space and makes routing more difficult.

More balanced part sizes (i.e., use small passives with small ICs) makes the layout work easier and the result will be better as well.

Use the largest C is smallest package per pin, do not add another ceramic for "bulk". If you want additional bulk, then use a considerably larger high-ESR type, like a tantalum or electrolytic.

[soFPG]

Yes, those are 0805 caps (and resistors). The time I started designing my own PCBs I bought a bunch of 0805 components and I honestly don't want to waste them.

Larger parts usually don't fit close, forcing you to do longer routing, which is bad for power integrity

I don't know much about PCB design theory but I have a hard time imagining that 2mm shorter traces (at most) would make a drastic difference.

do not add another ceramic for "bulk". If you want additional bulk, then use a considerably larger high-ESR type, like a tantalum or electrolytic.

Okay, thank you for that hint. Do you have information about why that is?

[EEVblog]

I have shot a video on this with layout comments, editing now...

[EEVblog]

Video just for you!

[Siwastaja]

Yes, those are 0805 caps (and resistors). The time I started designing my own PCBs I bought a bunch of 0805 components and I honestly don't want to waste them.

You are designing in FPGAs and image sensors, in range of $10, and you are concerned about literally $0.001 parts?

Don't worry, you will use your 0805 parts eventually in prototyping and projects where larger case sizes make sense.

Do yourself a favour and buy a large bag of 0402 caps for <=5V power decoupling, you are going to use them in every project. 0.1uF is the classical choice but I'd suggest get a larger value, it doesn't hurt and may help if you have some special cases where a lot of IOs switch with high edge rates; or if you want to satisfy the higher total capacitance suggestion on some datasheets without using multiple different values in parallel. Contrary to common misbelief, there is no downside, having a larger C doesn't make it a "lower frequency capacitor", the decoupling capability at high frequencies is only defined by the case size, the smaller the better. It only gets worse when you go such high C values that parts are not available in the small case size anymore.

I don't know much about PCB design theory but I have a hard time imagining that 2mm shorter traces (at most) would make a drastic difference.

Well, likely not that much, in the end. Bond wires add some 1-2mm as well so there is on-chip decoupling. It likely works just fine. But think about it that way, the chip is designed to decouple above about 100MHz internally, to cope with the inevitable ~5mm loop area (bond wires, capacitor package size, routing to that cap). Now if you add excess 2*2mm the manufacturer didn't expect, you have almost doubled the inductance the chip was designed to work with.

I would do it properly, to remove or reduce the unknowns. You will have to debug things anyway and it's easier if you can trust the power source. FPGAs and image sensors likely have higher edge rates than some PIC microcontrollers, so decoupling is more critical.

If using larger parts further away helped your design, I would accept the reduced power integrity as a tradeoff; maybe a stupid one, but a tradeoff anyway. But my point is, using smaller parts closer to each other will make your routing actually easier, leaving more space for routing the signals, so it's a win-win. The only downside is handsoldering, but seeing you are expecting to be able to solder the small pitch image sensor and the large pin count QFP FPGA, 0402 passives are totally piece of cake.

do not add another ceramic for "bulk". If you want additional bulk, then use a considerably larger high-ESR type, like a tantalum or electrolytic.

Okay, thank you for that hint. Do you have information about why that is?

To avoid resonances between different values of high Q factor capacitors, and, well, because there is no benefit but there is added complexity (and added line in BOM). See the recent thread https://www.eevblog.com/forum/projects/power-decoupling-myths/

If you want to ensure that you satisfy the total capacitance requirement, just increase the C. So for example, if the manufacturer recommends 10x 0.1uF + 1x1uF = total of 2uF, instead use 10x0.22uF or 10x0.47uF or even 10x1uF. In the smallest case you can get so that they perform well on high frequencies. Now you satisfy the requirement for the capacitance, and it will be lower inductance than if you had placed a large capacitor on a fairly random place (they never specify near which pins you should put that large cap), and you avoid resonances between the caps, and you saved a component, some board area, and a BOM line!

[soFPG]

Video just for you!

Thank you so much! I can't believe that's actually happening 

This helps me tremendously as I am just starting to get into more serious PCB layouts.

[EEVblog]

Yes, those are 0805 caps (and resistors). The time I started designing my own PCBs I bought a bunch of 0805 components and I honestly don't want to waste them.

You are designing in FPGAs and image sensors, in range of $10, and you are concerned about literally $0.001 parts?
Don't worry, you will use your 0805 parts eventually in prototyping and projects where larger case sizes make sense.
Do yourself a favour and buy a large bag of 0402 caps for <=5V power decoupling, you are going to use them in every project.

Not such a great blanket idea. 0402's are harder to place and inspect by both hand and machine.
0402 is the size where you have to have 0402 specific assembly machines (with good yield), and that can often rule out a lot of cheaper assembly houses, cheaper older production lines, backyard operators etc.
I'd only use 0402 if you have to for density reasons. 0603 and 0805 for everything else.