FET Gate source leakage current with temperature

[opampsmoker]

Hi,
The SISA40DN FET has 100nA of  gate_source leakage current at 25degc.
Do you know what it is at 85degC?....roughly.?

SISA40DN Mosfet:
https://www.vishay.com/docs/76681/sisa40dn.pdf

[Cerebus]

No, it has a datasheet maximum I_GSS leakage current of 100nA - which is high enough that I wouldn't trust that figure for a minute. Note that they don't give minimum and typical figures. That's probably a "we don't really test or characterise this in production, except to check that it's not broken" figure. I suspect the real figure, if measured, would be on the order of a few nanoamps or possibly even lower - assuming there's no gate protection zener, which with a quick glance at the datasheet there doesn't seem to be.

So, if you're actively making use of this figure you need a better source of data - which probably means measuring it yourself.

MOSFET I_GSS leakage current doesn't have a strong temperature dependance at typical operating temperatures (e.g. <= 150ºC), unlike  I_DSS. This isn't really surprising if you consider that a MOSFET set up for I_GSS measurement (source and drain shorted) looks like a small value glass capacitor with a low breakdown voltage and is going to have similar characteristics. I don't think I've even seen a graph of I_GSS versus temperature for an unprotected gate MOSFET (for protected gate MOSFETs the leakage characteristics of the protection diodes swamp the inate gate chracteristics and you can find these plotted in some datasheets).

[opampsmoker]

assuming there's no gate protection zener, which with a quick glance at the datasheet there doesn't seem to be.

Thanks for mentioning this....this is what it all boils down to it seems.
The datasheet doesnt say whether its got a gate_source zener so we cannot know...so we live in peril.
Our gate drive is so weak that we cant tolerate much higher than a few uA of leakage current from Gate to source.

If there is a gate-source zener, then at 85degc, the leakage would be 32 * 100nA = 6.4uA and this kills us.

[Cerebus]

I think you can assume that it doesn't have gate protection unless the datasheet explicitly calls it out. A proper read of the datasheet will tell you that, I just glanced at it.

[opampsmoker]

Thanks,
It seems strange that the "intrinsic" gate_source zener (in a FET) should have potentially high leakage current. -Becuase  discrete zeners dont have high leakage current...
For example, we have a UDZV8.2 (8.2V) zener on the fet gate, and its datasheet says it only has a maximum of 1nA of reverse current...even at 125degc.

UDZV8.2 Zener diode datasheet
https://fscdn.rohm.com/en/products/databook/datasheet/discrete/diode/zener/udzvte-178.2b-e.pdf

I wonder why the "Intrinsic" gate_source zener found in mosfets is said to be  so leaky of current?

[Zero999]

There's nothing "intrinsic" about a MOSFET gate protection zener. Plenty of MOSFETs lack one and work perfectly. Some MOSFETs have one added to improve ESD resistance. I agree, a gate protection zener shouldn't be any more leaky than any other zener diode.

The SISA40DN is cheap enough that you can destructively test one by gradually increasing the gate-source voltage, until either the zener conducts, or the gate fails. If it has a protection zener, then the gate should act like a zener diode, rather than a spark gap and the device should still work afterwards. Obviously, limit the current with a suitable resistor, otherwise the protection zener will still cook.

The gate leakage could theoretically be tested by applying a voltage to the gate and see how long it remains charged for, after it's left open circuit. You could measure the drain source resistance to see how long it takes to increase, as the gate discharges. I imagine such a set-up would be very sensitive to stray electric fields and would have to be conducted in a shielded enclosure.

[opampsmoker]

I imagine such a set-up would be very sensitive to stray electric fields and would have to be conducted in a shielded enclosure.

Hi, this is very interesting.....supposing we do this.....ie charge the gate up to 7V and then just leave the gate_source open circuit with the 7v on it......there is 3nF of CISS capacitance.....do you think a stray electric field could pull enough charge out of that 3nF capacitance to discharge the 3nF by more than 0.3V say?

[TimFox]

As Cerebus pointed out above, that leakage value is a guaranteed maximum.  In order to guarantee a value, it must be measured on automatic test equipment at high speed in production, and there is a limit to the sensitivity of current measurements in this process.  If you measure low leakage currents yourself with appropriate equipment, it will take more time than can be used economically on a production line.

[Cerebus]

The LMC662 operational amplifier has a maximum input bias current of 2 pA, and a typical input bias current of 2 fA (a thousand times smaller) and costs £1.35 for one off. The LMC6001 has an individually tested guaranteed input bias current of 25 fA and costs £13.40 for one off.

The two different parts are almost identical internally, the significant difference is that the LMC6001 spends enough time on a test rig to guarantee that low input bias current and that extra testing time is what makes one part cost ten times what the other does. The bias currents are almost entirely made up from the gate leakage currents in the input MOSFETs in these OPAs plus the leakage currents in their protection diodes.

One ampere is \$6.2415090744 \times 10^{18}\$ electrons a second, so 1 fA is \$6,241\$ electrons a second, so it should be obvious that fA current measurement is, shall we say, challenging.  In this video you can watch Bob Pease and Paul Groehe (spelling?) discuss the design of the initial laboratory test rig used for qualifying the LMC6001 at National Semiconductor. In particular you can see the lengths they had to go to to shield the DUT from external electric fields to make measurements at this current level possible.


(The discussion of femtoampere current measurement starts at 13 minutes in.)

[David Hess]

If I was that concerned about the behavior of the gate leakage current, I would test a few parts and measure it at different temperatures.

[Damianos]

The gate leakage current, for normal operation of this transistor, is not specified.
The I_GSS value, given in the data-sheet, is at the limits of V_GS. So, I think, we can take it as the way that they define the voltage limits of the gate. The same way, they define the V_DS breakdown and the V_GS(th); they specify a current limit and test at what voltage it happens.

...
Our gate drive is so weak that we cant tolerate much higher than a few uA of leakage current from Gate to source.
...

As your application seems as a linear operation of the transistor, you can make a simple test, for a draft estimation of the gate current. Use a variable source to drive the gate for a given output, for example I_D=0.5A and V_DS=2V and note the drive voltage. Next use a high value resistor (10 to 100 MOhms), adjust the drive voltage so to have the same output and note the new drive voltage. As the conditions (voltages, currents and temperature) are the same, the difference of the two drive voltages divided by the resistor value gives a draft estimation of the gate current.