Ethernet bit rate

[radiolistener]

Inputs between 0 and 0.8 or between 2.4 and 5 Volts do not result in any undefined state.  They are interpreted bythe chip as '0' and '1' inputs respectively.

And? That threshold range is intended for proper processing of digital signal which may have some interference and offset. But if you put some value from 0.8 to 2.4 V, it may enter into undefined state and after some delay exit to a random output. That behavior is not digital.

So if you use analog signal on the input, it cannot work as proper digital element.

If you want to digitize analog signal, it's better to use analog comparator instead of logic gate. Digital logic gate is not intended to work with analog signal.

[wasedadoc]

What happens when the input is between 0.8 and 2.4 Volts is not germane to any of the points I have made.  It is not a component of anything I have written.

You have not addressed my question of how the gate maps the ranges 0 to 0.8 and 2.4 to 5 Volts to logical 0 and 1 respectively.

[radiolistener]

You have not addressed my question of how the gate maps the ranges 0 to 0.8 and 2.4 to 5 Volts to logical 0 and 1 respectively.

if that values taken from datasheet, then this is valid threshold for a digital signal. So, when input signal is within valid range, it is assumed as digital signal. When it goes outside valid range for a digital signal, it is no more digital.

The digital signal has two fixed valid signal ranges. One for digital 1 and one for digital 0.

As you understand, 1000BASE-T ethernet signal is not compatible with digital signal, because it is analog signal and needs to be passed through analog frontend and converted into digital signal with ADC before processing in digital circuit.

[alm]

if that values taken from datasheet, then this is valid threshold for a digital signal. So, when input signal is within valid range, it is assumed as digital signal. When it goes outside valid range for a digital signal, it is no more digital.

So let's define a digital signal with 0 = 0-1 V, 1 = 1.25-2.25 V, 2 = 2.5-3.5 V and 3=3.75-4.75V. An IC with a digital input with these specifications is just as much, or as little, an ADC as any 74 series logic IC.

The digital signal has two fixed valid signal ranges. One for digital 1 and one for digital 0.

No, you're confusing the words digital and binary here. A binary signal is a digital signal with two valid signal ranges. One for binary 1 and one for binary 0. I appreciate that English may not be your native language, like for many on this forum, but try to get the technical terms right, and don't invent your own definitions.

[radiolistener]

So let's define a digital signal with 0 = 0-1 V, 1 = 1.25-2.25 V, 2 = 2.5-3.5 V and 3=3.75-4.75V.

Digital signal cannot have value other than 0 or 1. Did you ever seen digital logic element which accepts 0, 1, 2 and 3?

An IC with a digital input with these specifications is just as much, or as little, an ADC as any 74 series logic IC.

No. Digital logic element doesn't have ADC. Digital circuit such as 74 series works with binary signal 0 and 1.

ADC/DAC is not digital and is not analog device, ADC/DAC is a mixed signal device which works on boundary between digital and analog signal domain.

No, you're confusing the words digital and binary here.

If you're think that the digital signal can have other values than 0 and 1, then please show me example of such digital circuit which accepts not binary signal values such as 0,1,2,3.

Can you please show me some example of digital logic gate which can differentiate 0,1,2,3 discrete values on it's digital input pin?

For example I have digital input pins on FPGA Cyclone IV. Can you please show me, how can I accept and process values other than digital 0 and 1 from these digital pins?

I appreciate that English may not be your native language

English language doesn't matter here, because my native language has the the same difference between digital and binary terms. But digital circuit works with digital signal which is represented as a binary signal state 0 or 1.

Technically you can say that ternary signal is digital, because it also is represented as discrete digits. But in usual meaning digital signal means binary signal, because there is no electronic components for ternary signals. If you want to process ternary signal it's more easy to use ADC to convert it into usual digital binary representation and process it with usual digital binary logic elements.

[radiolistener]

But again, when we talking about ethernet signal it cannot be represented with discrete signal represented with just 5 levels. It has more levels, because there is also signal attenuation which is used by PHY for tuning signal power during link negotiation. And there is a sum of local TX and remote TX signals on the same pairs (both 5-level) + cable attenuation for remote TX. It's hard to name such complex analog signal as discrete, because it has too many possible levels.

[redkitedesign]

But again, when we talking about ethernet signal it cannot be represented with discrete signal represented with just 5 levels.

We're still talking about 1000BASE-T right? You should google an eye diagram once. Or measure one yourself.

You'll quickly notice two things:
- It has really recognizable discrete levels
- There are 4 levels, not 5.

[radiolistener]

You'll quickly notice two things:
- It has really recognizable discrete levels

Can you recognize TX and RX signals on the pair?

Also, when you looking at waveform, the link between PHY is already established, so the signal gain is already tuned and remains constant. But it doesn't means that it cannot be different if line characteristics will be changed.

For example see the datasheet for RTL8211E 10/100/1000M Ethernet PHY transceiver, page 18:

In 1000/100Mbps mode the RTL8211E-VB(VL)/RTL8211EG-VB provides dynamic detection of cable length and dynamic adjustment of power required for the detected cable length. This feature provides intermediate performance with minimum power consumption.

Do you really think that transmitter output signal power adjustment is possible for 5-level discrete signal with fixed 5-levels output?

The same for receiver, remote PHY can have different output signal power and the cable length may be different, so it has different attenuation. Do you really think that ADC which can recognize just fixed 5 levels is enough here?

- There are 4 levels, not 5.

I already posted 1000BASE-T signal waveform, I can see at least 11 levels here:



How about 4 levels? Can you explain it? 

[redkitedesign]

I already posted 1000BASE-T signal waveform, I can see at least 11 levels here:

How about 4 levels? Can you explain it? 

It's not an eye-diagram. There is a reason telecommunications engineers like eye-diagrams. They are much more informative than a random waveform.

[radiolistener]

It's not an eye-diagram. There is a reason telecommunications engineers like eye-diagrams. They are much more informative than a random waveform.

But it still clear that there is more than 5 levels and this is 1000BASE-T signal with PAM5. Can you explain it?

[redkitedesign]

But it still clear that there is more than 5 levels. Can you explain it?

You're looking at noise and transients. Not at the relevant part of the signal. That's why you use an eye-diagram.

[radiolistener]

it's pretty clear from waveform that these levels are not noise, you can see noise and it's amplitude is much less than visible level step.

[radiolistener]

Here is eye diagram of 1000BASE-T signal. Can you explain why it has more than 4 levels as you claimed?

[redkitedesign]

Here is eye diagram of 1000BASE-T signal. Can you explain why it has more than 4 levels as you claimed?

Because it isn't a regular 1000BASE-T Eye, but a transmitter distortion test.

You might as well post an image of a duck and ask why it doesn't explain you how to find the beach.

[radiolistener]

Because it isn't a regular 1000BASE-T Eye, but a transmitter distortion test.

And how is it possible if transmitter output has just 4 fixed levels, as you claimed?

The question we're talking about if we can name 1000BASE-T signal as digital or analog.

[mikerj]

Here is eye diagram of 1000BASE-T signal. Can you explain why it has more than 4 levels as you claimed?

You have shown an eye diagram output of a device running in test mode 4.  This uses a digital filter to apply a deliberate inter-symbol interference to the PAM5 signal which generates the 17 levels shown in your post.

The normal PAM-5 eye diagram looks like this:

[radiolistener]

mikerj

Thanks. What is your thoughts - is 1000BASE-T pair line is digital or analog?

[mikerj]

mikerj

Thanks. What is your thoughts - is 1000BASE-T pair line is digital or analog?

It's an analog voltage representing a digital value, and this is the same even if you are talking about regular two state TTL logic.

[radiolistener]

It's an analog voltage representing a digital value, and this is the same even if you are talking about regular two state TTL logic.

Please clarify - can it be processed with a digital input pin on FPGA? Or it needs to be processed with analog input on ADC first?

How to handle it properly - as analog, or as digital?

[Siwastaja]

While 1000BASE-T PAM-5 modulated signal can't be connected to a "digital input of an FPGA", it can NOT be connected to "an analog input" of "an ADC" either. It is connected to a 1000BASE-T PHY, which is not an ADC, but a 1000BASE-T PHY (which may contain an ADC or may not, depending on the definitions used.)

You need to get over the fixation of classifying every detail in either analog or digital mental bin. It makes no sense to force every term and concept through such classification at all. And further, analog and digital are not opposites and they are not non-overlapping. Correct answer is, digital data is represented by voltage which carries analog-world phenomena. Communication buses which carry digital data which can be recovered to the same numbers as sent are called digital communication buses, 1000BASE-T and SPI being two examples with multi-level and 2-level (binary) encodings, respectively. They are both digital buses because you put in numbers, you receive numbers. This does not mean numbers have to be physically on the bus; as a number is an abstract concept, this is not possible, and no one is claiming that. Numbers are represented as electrical signals, and this is no different even if you vary number of voltage levels used to convey different symbols.

If you insist on calling multi-level input circuitry an "ADC", then there is absolutely no reason not to call a standard binary CMOS logic input a 1-bit (2-level) ADC as well, therefore rendering your I2C or SPI as much analog as 1000BASE-T is.

[wasedadoc]

Anyone who has designed PCBs for high speed digital chips knows well that even the binary data signals between the chips have to be treated as analogue.  All the analogue impairments such as noise, crosstalk, ground bounce, ringing, reflections, impedance mismatch etc can come into play.  There is an eye diagram.  It may be simpler than the multi-opening one for GigE but the principle is no different.

[mikerj]

It's an analog voltage representing a digital value, and this is the same even if you are talking about regular two state TTL logic.

Please clarify - can it be processed with a digital input pin on FPGA? Or it needs to be processed with analog input on ADC first?

How to handle it properly - as analog, or as digital?

How to process a simple TTL level digital signal running at 1Gbit/s? Can it be processed with a a simple GPIO pin after being sent down 100m of cable?

Using a high speed ADC permits digital processing to compensate for the distortions that dominate high speed comms systems.  If you you were only passing a PAM-5 signal a short distance you could absolutely design a 5 level logic input that would decode it.

It seems to me that you are trying to say that that "digital" == "binary", which simply isn't the case.  The flash memory in modern SSDs use multi-level cells to store more than one bit per cell, does that mean the information is no longer digital?

[radiolistener]

How to process a simple TTL level digital signal running at 1Gbit/s? Can it be processed with a a simple GPIO pin after being sent down 100m of cable?

We have differential digital input on FPGA, and can use some driver to match it's digital level with voltage selected for digital input on FPGA.

The question is - if we can process signal waveform presented on 1000BASE-T pair as digital, or we need to treat it as analog in order to properly decode or encode it?

If you you were only passing a PAM-5 signal a short distance you could absolutely design a 5 level logic input that would decode it.

Can we handle it with digital GPIO on FPGA? Do we needs ADC and DAC in order to receive and send data with PAM-5? Or we can do it directly as digital signal on digital GPIO?

It seems to me that you are trying to say that that "digital" == "binary", which simply isn't the case.  The flash memory in modern SSDs use multi-level cells to store more than one bit per cell, does that mean the information is no longer digital?

Yes it represents digital information, but it stores it in analog state. Isn't it?

There is reverse situation, we can store and process analog signal in digital domain, in such case it is processed as binary state signals, but it represents analog signal. Does it means that DSP which perform digital signal processing is analog circuit? No. It is digital.

I just assume that digital signal/circuit means that it works with binary state of signal. If some element has analog and digital input/output it is assumed as mixed signal. Isn't it?

If I'm wrong, can you please show me clean digital circuit (not mixed signal) which works with signal which is not binary and can have many voltage levels?

I think if such digital circuit which can work with multi-level signals doesn't exists in the whole world, there is no sense to say that multi-level signal is digital, because it can't be processed as digital in the usual sense and needs to be treated as analog signal.

Anyone who has designed PCBs for high speed digital chips knows well that even the binary data signals between the chips have to be treated as analogue.

yes, but if this is a digital circuit it expects two state on the analog line 0 or 1.
If digital circuit is unable to keep signal levels within digital thresholds for 0 and 1, it fails and no longer digital.
Can you show me example of digital circuit which use logic gates which accept and can differentiate 5 separate voltage levels instead of 2?

It is connected to a 1000BASE-T PHY, which is not an ADC, but a 1000BASE-T PHY (which may contain an ADC or may not, depending on the definitions used.)

I'm sure it consists ADC and DAC inside and use DSP in digital domain where binary signals are used.

And, after all, PHY chip is not required element in order to establish 1000BASE-T link. You can do it with your own circuit, but it won't works with simple high speed digital input/output. You're needs to add ADC and DAC to apply conversion between analog domain of 1000BASE-T line and digital domain of DSP which process it as binary signals. Isn't it?

[radiolistener]

All the analogue impairments such as noise, crosstalk, ground bounce, ringing, reflections, impedance mismatch etc can come into play. 

There is another example. We have old-school analog amplifier on tubes with analog equalizer on the input. Does it means that this analog amplifier turns into digital just because we put on its input the music from 24-bit DAC?

Can we assume 24-bit DAC analog output as digital? Just because it has fixed 16777216 voltage levels
If you assume 5 level signal as digital, then why signal with 16777216 levels is not digital and marked as analog on ADC output?

Where is the limit in your model? The signal with 256 voltage levels is digital or analog?

[redkitedesign]

How to process a simple TTL level digital signal running at 1Gbit/s? Can it be processed with a a simple GPIO pin after being sent down 100m of cable?

I once did a project where we used two digital outputs and a differential input of an FPGA to implement a E1 interface.

E1 was a (mostly non-US) digital, 2.048MBit communications interface that predated fiber, DSL and other high-speed internet access tech. It used a mixture of positive and negative pulses (so strictly speaking, three-level) over a twisted pair (standard telephone line).

Using the outputs as open drain on the outsides of a center-tapped (and supplied!) transformer we could generate the positive and negative pulses.
Using a differential input with some proper biasing resistors we could detect either positive or negative pulses. With some logic we could make a clock recovery, and thus deduce what the undetected pulses were.

And with an internal 200MHz clock we could make the pulses meet the (rather strict) pulse-length requirement.

Worked pretty good, even met the ITU spec.  But you needed 4 200MHz capable pins to make one 2MBit interface.....